公开(公告)号：US12119063B2

公开(公告)日：2024-10-15

申请号：US17957532

申请日：2022-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan Nam ,  Hyunggon Kim ,  Bong-Kil Jung ,  Younho Hong ,  Juseong Hwang

IPC: G11C16/08

CPC classification number: G11C16/08

Abstract: Disclosed is a memory device includes a memory block that is connected with a plurality of wordlines, a voltage generating circuit configured to output a first non-selection voltage through a plurality of driving lines, and an address decoding circuit configured to connect the plurality of driving lines with unselected wordlines of the plurality of wordlines. During a wordline setup period for the plurality of wordlines, the voltage generating circuit floats first driving lines corresponding to first unselected wordlines of the unselected wordlines from among the plurality of driving lines when the first unselected wordlines reach a first target level, and floats second driving lines corresponding to second unselected wordlines of the unselected wordlines from among the plurality of driving lines when the second unselected wordlines reach a second target level different from the first target level.