公开(公告)号：US20230229841A1

公开(公告)日：2023-07-20

申请号：US18151051

申请日：2023-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae JANG ,  Jongwon KIM ,  In HUH ,  Satbyul KIM ,  Younggu KIM ,  Yunjun NAM ,  Changwook JEONG ,  Moonhyun CHA

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F2119/02

Abstract: A method for simulating a layout of an integrated circuit manufactured by a semiconductor process includes extracting a plurality of pattern layouts from layout data that defines the layout, generating training data by amplifying the plurality of pattern layouts and at least one parameter provided from the semiconductor process, generating sample data by sampling the training data, generating feature data including a three-dimensional array from the sample data, providing the sample data and the feature data to a simulator and a machine learning model, respectively, and training the machine learning model based on an output of the machine learning model and an output of the simulator.