公开(公告)号：US20230229841A1

公开(公告)日：2023-07-20

申请号：US18151051

申请日：2023-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae JANG ,  Jongwon KIM ,  In HUH ,  Satbyul KIM ,  Younggu KIM ,  Yunjun NAM ,  Changwook JEONG ,  Moonhyun CHA

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F2119/02

Abstract: A method for simulating a layout of an integrated circuit manufactured by a semiconductor process includes extracting a plurality of pattern layouts from layout data that defines the layout, generating training data by amplifying the plurality of pattern layouts and at least one parameter provided from the semiconductor process, generating sample data by sampling the training data, generating feature data including a three-dimensional array from the sample data, providing the sample data and the feature data to a simulator and a machine learning model, respectively, and training the machine learning model based on an output of the machine learning model and an output of the simulator.

公开(公告)号：US20220207431A1

公开(公告)日：2022-06-30

申请号：US17460698

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung PARK ,  Changwook JEONG ,  Moonhyun CHA

IPC: G06N20/20 ,  G06K9/62

Abstract: A computer-implemented method of training a teacher model and a student model includes dividing the teacher model into a series of teacher blocks each comprising at least one layer; generating a first student branch receiving a first feature output from a first teacher block among the series of teacher blocks; training the teacher model based on outputs of the teacher model and the first student branch; and training the student model comprising a series of student blocks based on the trained teacher model, wherein the first student branch includes at least one student block.

公开(公告)号：US20210174201A1

公开(公告)日：2021-06-10

申请号：US16907780

申请日：2020-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： In HUH ,  Sanghoon MYUNG ,  Wonik JANG ,  Changwook JEONG

IPC: G06N3/08 ,  G06K9/62 ,  G06N5/04

Abstract: A computing device includes memory storing computer-executable instructions; and processing circuitry configured to execute the computer-executable instructions such that the processing circuitry is configured to operate as a machine learning generator configured to receive semiconductor process parameters, to generate semiconductor process result information from the semiconductor process parameters, and to output the generated semiconductor process result information; and operate as a machine learning discriminator configured to receive the generated semiconductor process result information from the machine learning generator and to discriminate whether the generated semiconductor process result information is true.

公开(公告)号：US20210056425A1

公开(公告)日：2021-02-25

申请号：US16910908

申请日：2020-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwook JEONG ,  Sanghoon Myung ,  In Huh ,  Hyeonkyun Noh ,  Minchul Park ,  Hyunjae Jang

IPC: G06N3/08 ,  G06N20/00 ,  G06K9/62

Abstract: A method for a hybrid model that includes a machine learning model and a rule-based model, includes obtaining a first output from the rule-based model by providing a first input to the rule-based model, and obtaining a second output from the machine learning model by providing the first input, a second input, and the obtained first output to the machine learning model. The method further includes training the machine learning model, based on errors of the obtained second output.

公开(公告)号：US20200175665A1

公开(公告)日：2020-06-04

申请号：US16599733

申请日：2019-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul PARK ,  Ami MA ,  Jisu RYU ,  Changwook JEONG

IPC: G06T7/00 ,  H01L21/67 ,  G01N21/956 ,  G06T5/00 ,  G01N21/95

Abstract: A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.

公开(公告)号：US20190385695A1

公开(公告)日：2019-12-19

申请号：US16249543

申请日：2019-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwook JEONG ,  Sanghoon MYUNG ,  Min-Chul PARK ,  Jeonghoon KO ,  Jisu RYU ,  Hyunjae JANG ,  Hyungtae KIM ,  Yunrong LI ,  Min Chul JEON

IPC: G11C29/50 ,  G11C29/48 ,  G11C29/56 ,  G01R31/27 ,  G01R31/26 ,  G01R31/3185 ,  G01R31/30

Abstract: A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

公开(公告)号：US20220374498A1

公开(公告)日：2022-11-24

申请号：US17672060

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changwook JEONG ,  Dongjin LEE ,  Kijung SHIN

IPC: G06F17/16

Abstract: A tensor data processing method is provided. The method comprises receiving an input tensor including at least one of an outlier and a missing value, the input tensor being input during a time interval between a first time point and a second time point, factorizing the input tensor into a low rank tensor to extract a temporal factor matrix, calculating trend and periodic pattern from the extracted temporal factor matrix, detecting the outlier which is out of the calculated trend and periodic pattern, updating the temporal factor matrix except the detected outlier, combining the updated temporal factor matrix and a non-temporal factor matrix of the input tensor to calculate the real tensor and recovering the input tensor by setting data corresponding to a position of the outlier or a position of the missing value of the input tensor from the data of the real tensor as an estimated value.

公开(公告)号：US20210158173A1

公开(公告)日：2021-05-27

申请号：US16909132

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonik JANG ,  Sanghoon MYUNG ,  Changwook JEONG ,  Sunghee LEE

IPC: G06N3/08 ,  G06N3/04

Abstract: A non-transitory computer-readable medium storing a program code including an image generation model, which when executed, causes a processor to input input data including sampling data of some of a plurality of semiconductor dies of a wafer to a generator network of the image generation model and output a wafer map indicating the plurality of semiconductor dies, and to input the wafer map output from the generator network to a discriminator network of the image generation model and discriminate the wafer map.