公开(公告)号：US20220366122A1

公开(公告)日：2022-11-17

申请号：US17572860

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonnyung Lee ,  Yeongjun Kwon ,  Jaeyong Shin ,  Jeonghoon Ahn ,  Yunki Choi

IPC: G06F30/3953 ,  H01L23/528

Abstract: A method of designing an interconnect structure of a semiconductor apparatus is provided. The interconnect structure includes interconnection layers sequentially stacked on a semiconductor substrate, and each of the interconnection includes dummy metal patterns and main metal patterns. The method includes: determining a layout of the main metal patterns included in each of the plurality of interconnection layers; determining a number of interconnection layers in the plurality of interconnection layers; and determining a layout of the dummy metal patterns included in each of the plurality of interconnection layers based on the determined layout of the main metal patterns and the determined number of interconnection layers.

公开(公告)号：US12159095B2

公开(公告)日：2024-12-03

申请号：US17572860

申请日：2022-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonnyung Lee ,  Yeongjun Kwon ,  Jaeyong Shin ,  Jeonghoon Ahn ,  Yunki Choi

IPC: G06F30/392 ,  G06F30/3953 ,  H01L23/528

Abstract: A method of designing an interconnect structure of a semiconductor apparatus is provided. The interconnect structure includes interconnection layers sequentially stacked on a semiconductor substrate, and each of the interconnection includes dummy metal patterns and main metal patterns. The method includes: determining a layout of the main metal patterns included in each of the plurality of interconnection layers; determining a number of interconnection layers in the plurality of interconnection layers; and determining a layout of the dummy metal patterns included in each of the plurality of interconnection layers based on the determined layout of the main metal patterns and the determined number of interconnection layers.

公开(公告)号：US11429777B2

公开(公告)日：2022-08-30

申请号：US17213538

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonji Park ,  Jeonghoon Ahn ,  Jihyung Kim ,  Jaehee Oh ,  Yunki Choi ,  Minguk Kang

IPC: G06F30/398 ,  G06F30/392 ,  H01L21/66 ,  G06F113/18 ,  G06F119/08 ,  G06F119/18

Abstract: A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model.

公开(公告)号：US12107034B2

公开(公告)日：2024-10-01

申请号：US17517291

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shaofeng Ding ,  Sungwook Moon ,  Jeonghoon Ahn ,  Yunki Choi

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A semiconductor chip may include; a device layer including transistors on a substrate, a wiring layer on the device layer, a first through via passing through the device layer and the substrate, and a second through via passing through the wiring layer, the device layer and the substrate, wherein a first height of the first through via is less than a second height of the second through via.

公开(公告)号：US20220035984A1

公开(公告)日：2022-02-03

申请号：US17213538

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonji Park ,  Jeonghoon Ahn ,  Jihyung Kim ,  Jaehee Oh ,  Yunki Choi ,  Minguk Kang

IPC: G06F30/392 ,  H01L21/66 ,  G06F30/398 ,  G06F119/08 ,  G06F113/18 ,  G06F119/18

Abstract: A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model.