公开(公告)号：US20220366122A1

公开(公告)日：2022-11-17

申请号：US17572860

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonnyung Lee ,  Yeongjun Kwon ,  Jaeyong Shin ,  Jeonghoon Ahn ,  Yunki Choi

IPC: G06F30/3953 ,  H01L23/528

Abstract: A method of designing an interconnect structure of a semiconductor apparatus is provided. The interconnect structure includes interconnection layers sequentially stacked on a semiconductor substrate, and each of the interconnection includes dummy metal patterns and main metal patterns. The method includes: determining a layout of the main metal patterns included in each of the plurality of interconnection layers; determining a number of interconnection layers in the plurality of interconnection layers; and determining a layout of the dummy metal patterns included in each of the plurality of interconnection layers based on the determined layout of the main metal patterns and the determined number of interconnection layers.

公开(公告)号：US20240222421A1

公开(公告)日：2024-07-04

申请号：US18603529

申请日：2024-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihyung KIM ,  Jeonghoon Ahn ,  Jaehee Oh ,  Shaofeng Ding ,  Wonji Park ,  Jegwan Hwang

IPC: H01G4/30 ,  H01L23/522

CPC classification number: H01L28/65 ,  H01L23/5223 ,  H01L28/87

Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.

公开(公告)号：US12159095B2

公开(公告)日：2024-12-03

申请号：US17572860

申请日：2022-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonnyung Lee ,  Yeongjun Kwon ,  Jaeyong Shin ,  Jeonghoon Ahn ,  Yunki Choi

IPC: G06F30/392 ,  G06F30/3953 ,  H01L23/528

Abstract: A method of designing an interconnect structure of a semiconductor apparatus is provided. The interconnect structure includes interconnection layers sequentially stacked on a semiconductor substrate, and each of the interconnection includes dummy metal patterns and main metal patterns. The method includes: determining a layout of the main metal patterns included in each of the plurality of interconnection layers; determining a number of interconnection layers in the plurality of interconnection layers; and determining a layout of the dummy metal patterns included in each of the plurality of interconnection layers based on the determined layout of the main metal patterns and the determined number of interconnection layers.

公开(公告)号：US11429777B2

公开(公告)日：2022-08-30

申请号：US17213538

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonji Park ,  Jeonghoon Ahn ,  Jihyung Kim ,  Jaehee Oh ,  Yunki Choi ,  Minguk Kang

IPC: G06F30/398 ,  G06F30/392 ,  H01L21/66 ,  G06F113/18 ,  G06F119/08 ,  G06F119/18

Abstract: A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model.

公开(公告)号：US20200343178A1

公开(公告)日：2020-10-29

申请号：US16596074

申请日：2019-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeonghoon Ahn

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L49/02 ,  H01L21/768

Abstract: A semiconductor device includes a first electrode disposed on a substrate. A capacitor dielectric layer is on the first electrode. A second electrode is on the capacitor dielectric layer. A first insulating layer is on the first and second electrodes and the capacitor dielectric layer. A first interconnection structure is on the first insulating layer and connected to the first electrode. A second interconnection structure is on the first insulating layer and connected to the second electrode. A second insulating layer is on the first and second interconnection structures. A plurality of connection structures are configured to pass through the second insulating layer and be connected to the first and second interconnection structures. Each of the first and second interconnection structures has an aluminum layer.

公开(公告)号：US12107034B2

公开(公告)日：2024-10-01

申请号：US17517291

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shaofeng Ding ,  Sungwook Moon ,  Jeonghoon Ahn ,  Yunki Choi

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A semiconductor chip may include; a device layer including transistors on a substrate, a wiring layer on the device layer, a first through via passing through the device layer and the substrate, and a second through via passing through the wiring layer, the device layer and the substrate, wherein a first height of the first through via is less than a second height of the second through via.

公开(公告)号：US11955509B2

公开(公告)日：2024-04-09

申请号：US17559176

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihyung Kim ,  Jeonghoon Ahn ,  Jaehee Oh ,  Shaofeng Ding ,  Wonji Park ,  Jegwan Hwang

IPC: H01L23/522 ,  H01L23/52 ,  H01L49/02

CPC classification number: H01L28/65 ,  H01L23/5223 ,  H01L28/87

Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.

公开(公告)号：US20220035984A1

公开(公告)日：2022-02-03

申请号：US17213538

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonji Park ,  Jeonghoon Ahn ,  Jihyung Kim ,  Jaehee Oh ,  Yunki Choi ,  Minguk Kang

IPC: G06F30/392 ,  H01L21/66 ,  G06F30/398 ,  G06F119/08 ,  G06F113/18 ,  G06F119/18

Abstract: A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model.

公开(公告)号：US20240178131A1

公开(公告)日：2024-05-30

申请号：US18382546

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunoo KIM ,  Shaofeng Ding ,  Jeonghoon Ahn ,  Jaehee Oh

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76813 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/05 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/04941

Abstract: A semiconductor device includes: a semiconductor substrate; an integrated circuit layer disposed on the semiconductor substrate; a first metal wiring layer to an n-th metal wiring layer sequentially disposed on the semiconductor substrate and the integrated circuit layer, wherein n is a positive integer; a plurality of wiring vias connecting the first to n-th metal wiring layers to each other, and a through-via extending in a vertical direction from a via connection pad, which is any one of the first metal wiring layer to the n-th metal wiring layer, toward the semiconductor substrate and penetrating the semiconductor substrate, wherein the via connection pad is a capping-type via connection pad formed on an upper surface of the through-via.

公开(公告)号：US20230148222A1

公开(公告)日：2023-05-11

申请号：US18050724

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boin Noh ,  Jeonghoon Ahn

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L24/08 ,  H01L25/0655 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L2224/08225 ,  H01L2924/3511 ,  H01L2924/182 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/1632

Abstract: An interposer structure includes: an interposer substrate; an interposer through electrode penetrating through the interposer substrate in a vertical direction; a redistribution structure on the interposer substrate and including a redistribution pattern connected to the interposer through electrode and a redistribution insulating layer on side surfaces of the redistribution pattern on the interposer substrate; a conductive post on the redistribution structure and connected to the redistribution pattern; and an interposer insulating layer on side surfaces of the conductive post on the redistribution structure.