公开(公告)号：US20240193323A1

公开(公告)日：2024-06-13

申请号：US18534184

申请日：2023-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yukihide TSUJI ,  Hisashi KOTAKEMORI ,  Shinwook YI ,  Yuntae LEE

IPC: G05B19/4099

CPC classification number: G05B19/4099 ,  G05B2219/45031

Abstract: A simulation method of a semiconductor process includes receiving first input data including values of a plurality of parameters received from the outside, setting a simulation using the plurality of parameters, improving the simulation by ordering the plurality of parameters, and executing the simulation by processing a job stored in a queue, wherein the optimizing includes generating a table with respect to the plurality of parameters, ordering the plurality of parameters based on the first input data, generating a job tree based on the plurality of ordered parameters, reconstructing the table based on the job tree, and generating the queue by storing the job in the queue based on the reconstructed table.

公开(公告)号：US20200335469A1

公开(公告)日：2020-10-22

申请号：US16822300

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghoon KIM ,  Jaehyun LIM ,  Yuntae LEE ,  Sayoon KANG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: Provided is a semiconductor package including a package structure including a base connection member including a redistribution layer, a first semiconductor chip including a plurality of first connection pads connected to the redistribution layer, an encapsulant disposed on the base connection member and covering at least a portion of the first semiconductor chip, and a backside connection member disposed on the encapsulant and including a backside wiring layer electrically connected to the redistribution layer, and a second semiconductor chip disposed on the base connection member or the backside connection member, the second semiconductor chip including a plurality of second connection pads connected to the redistribution layer or the backside wiring layer, the second semiconductor chip including a logic circuit, the first semiconductor chip including a logic input and output terminals that are connected to the logic circuit through at least one of the redistribution layer and the backside wiring layer.