公开(公告)号：US20210288000A1

公开(公告)日：2021-09-16

申请号：US17001992

申请日：2020-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuseon HEO

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

Abstract: A semiconductor package includes a frame, a semiconductor chip, a through via, a connection pad, a lower redistribution layer on the bottom surfaces of the frame and the semiconductor chip, a connection terminal on the lower redistribution layer, an encapsulant covering the top surfaces of the frame and the semiconductor chip, and an upper redistribution layer on the encapsulant. The lower redistribution layer includes a lower insulating layer, a lower redistribution pattern, and an under-bump metal (UBM). The upper redistribution layer includes an upper insulating layer, an upper redistribution pattern, an upper via, and an upper connection pad. The lower insulating layer includes an inner insulating pattern surrounding the side surface of the UBM and an outer insulating pattern surrounding the side surface of the inner insulating pattern. The cyclization rate of the inner insulating pattern is higher than the cyclization rate of the outer insulating pattern.

公开(公告)号：US20240136201A1

公开(公告)日：2024-04-25

申请号：US18381905

申请日：2023-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuseon HEO ,  Junhyeong Park ,  Jieun Park ,  Jihye Shim ,  Jiyoung Lee

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L21/4857 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/18 ,  H10B80/00 ,  H01L24/04

Abstract: Provided is a method of manufacturing a semiconductor package, the method including forming a first wiring structure, coating a high transmittance photoresist on the first wiring structure a plurality of number of times, forming a plurality of openings by exposing and developing the high transmittance photoresist, forming a plurality of conductive posts by filling the plurality of openings with a conductive material, removing the high transmittance photoresist, disposing a semiconductor chip on the first wiring structure, forming an encapsulant surrounding the semiconductor chip and the plurality of conductive posts, and forming a second wiring structure on the encapsulant, wherein the light transmittance of the high transmittance photoresist at a portion where the first wiring structure and the high transmittance photoresist contact each other is greater than or equal to 3.2%.

公开(公告)号：US20250087544A1

公开(公告)日：2025-03-13

申请号：US18367801

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuseon HEO

IPC: H01L23/31 ,  H01L23/00

Abstract: Provided is a semiconductor package including a first wiring structure including a plurality of first wiring patterns respectively including a plurality of first lower surface connection pads and a plurality of first upper surface connection pads, a second wiring structure including a plurality of second wiring patterns respectively including a plurality of second lower surface connection pads and a plurality of second upper surface connection pads, a semiconductor chip arranged between the first wiring structure and the second wiring structure, a plurality of connection structures connecting some of the plurality of first upper surface connection pads to the plurality of second lower surface connection pads, and arranged adjacent to the semiconductor chip, and a binding reinforcement layer on side surfaces of each of the plurality of connection structures and at least a portion of the semiconductor chip.

公开(公告)号：US20250054773A1

公开(公告)日：2025-02-13

申请号：US18431454

申请日：2024-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuseon HEO

IPC: H01L21/48 ,  C23C18/16 ,  C23C18/31 ,  C23C18/48 ,  C23C28/02 ,  C25D5/00 ,  C25D5/02 ,  C25D7/12 ,  G03F7/16 ,  G03F7/30 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H10B80/00

Abstract: A method of forming a plating pattern includes forming a first plating layer on a substrate, forming a photosensitive material layer on the first plating layer, patterning the photosensitive material layer to have a trench exposing a portion of the first plating layer, forming a superhydrophobic film on a surface of the photosensitive material layer, forming a second plating layer in the trench by immersing the photosensitive material layer and the first plating layer in a plating solution, and simultaneously removing the superhydrophobic film and the photosensitive material layer.

公开(公告)号：US20250118639A1

公开(公告)日：2025-04-10

申请号：US18672349

申请日：2024-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjo KIM ,  Junhyeong PARK ,  Sunhyung KIM ,  Jieun PARK ,  Jihye SHIM ,  Yuseon HEO

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a first redistribution structure including upper pads; a semiconductor chip disposed on the first redistribution structure; an encapsulant on the first redistribution structure and surrounding the semiconductor chip; a second redistribution structure disposed on the encapsulant and including an upper redistribution layer; a plurality of posts penetrating the encapsulant and electrically connecting the upper pads of the first redistribution structure to the upper redistribution layer of the second redistribution structure; metal layers between the upper pads and the plurality of posts and having an upper surface having a first step difference with an upper surface of an edge of the upper pads; and a seed layer between the metal layers and the plurality of posts.

公开(公告)号：US20240234165A9

公开(公告)日：2024-07-11

申请号：US18381905

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuseon HEO ,  Junhyeong Park ,  Jieun Park ,  Jihye Shim ,  Jiyoung Lee

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L21/4857 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/18 ,  H10B80/00 ,  H01L24/04

Abstract: Provided is a method of manufacturing a semiconductor package, the method including forming a first wiring structure, coating a high transmittance photoresist on the first wiring structure a plurality of number of times, forming a plurality of openings by exposing and developing the high transmittance photoresist, forming a plurality of conductive posts by filling the plurality of openings with a conductive material, removing the high transmittance photoresist, disposing a semiconductor chip on the first wiring structure, forming an encapsulant surrounding the semiconductor chip and the plurality of conductive posts, and forming a second wiring structure on the encapsulant, wherein the light transmittance of the high transmittance photoresist at a portion where the first wiring structure and the high transmittance photoresist contact each other is greater than or equal to 3.2%.

公开(公告)号：US20230014900A1

公开(公告)日：2023-01-19

申请号：US17956153

申请日：2022-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuseon HEO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/10

Abstract: A semiconductor package includes a frame, a semiconductor chip, a through via, a connection pad, a lower redistribution layer on the bottom surfaces of the frame and the semiconductor chip, a connection terminal on the lower redistribution layer, an encapsulant covering the top surfaces of the frame and the semiconductor chip, and an upper redistribution layer on the encapsulant. The lower redistribution layer includes a lower insulating layer, a lower redistribution pattern, and an under-bump metal (UBM). The upper redistribution layer includes an upper insulating layer, an upper redistribution pattern, an upper via, and an upper connection pad. The lower insulating layer includes an inner insulating pattern surrounding the side surface of the UBM and an outer insulating pattern surrounding the side surface of the inner insulating pattern. The cyclization rate of the inner insulating pattern is higher than the cyclization rate of the outer insulating pattern.