公开(公告)号：US20230025153A1

公开(公告)日：2023-01-26

申请号：US17867150

申请日：2022-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunhyeok CHOI ,  Yongki LEE ,  Sumin NOH ,  Jieun PARK ,  Bohdan KARPINSKYY

IPC: G06F7/58

Abstract: A random number generating circuit includes: an oscillation circuit including a plurality of first delay elements connected to each other in series to generate an oscillation signal; a sampling circuit including a plurality of second delay elements connected to each other in series to generate a plurality of sampling signals by sampling the oscillation signal at a plurality of sampling points in time based on the plurality of second delay elements; and a random number determining circuit configured to generate a random number based on a target sampling point in time associated with a target sampling signal in which a first logic level transition occurs from among the plurality of sampling signals, wherein the plurality of sampling points includes the target sampling point.

公开(公告)号：US20220128911A1

公开(公告)日：2022-04-28

申请号：US17340267

申请日：2021-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jieun PARK ,  Youngmin SEO ,  Inbeom YIM

IPC: G03F7/20 ,  H01L21/66

Abstract: A method of manufacturing a semiconductor device includes selecting a diffraction based focus (DBF) mark that is unaffected by a pattern of a lower layer; manufacturing a mask including a mark pattern for forming the DBF mark; forming the DBF mark in a cell region of a wafer by using the mask; measuring the DBF mark and monitoring defocus; correcting the defocus on the basis of a result of the monitoring; and forming a pattern in the cell region of the wafer, after correcting the defocus.

公开(公告)号：US20250118639A1

公开(公告)日：2025-04-10

申请号：US18672349

申请日：2024-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjo KIM ,  Junhyeong PARK ,  Sunhyung KIM ,  Jieun PARK ,  Jihye SHIM ,  Yuseon HEO

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a first redistribution structure including upper pads; a semiconductor chip disposed on the first redistribution structure; an encapsulant on the first redistribution structure and surrounding the semiconductor chip; a second redistribution structure disposed on the encapsulant and including an upper redistribution layer; a plurality of posts penetrating the encapsulant and electrically connecting the upper pads of the first redistribution structure to the upper redistribution layer of the second redistribution structure; metal layers between the upper pads and the plurality of posts and having an upper surface having a first step difference with an upper surface of an edge of the upper pads; and a seed layer between the metal layers and the plurality of posts.

公开(公告)号：US20160062798A1

公开(公告)日：2016-03-03

申请号：US14721517

申请日：2015-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeongtaek LEE ,  SEUNGKYU KIM ,  Jieun PARK ,  WonJoon JANG

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/4856 ,  G06F9/5027 ,  G06F9/5033 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/32

Abstract: A scheduling method of a system-on-chip including a multi-core processor includes detecting a scheduling request of a thread to be executed in the multi-core processor, and detecting a calling thread having the same context as the scheduling-requested thread among threads that are being executed in the multi-core processor. The method includes reassigning or resetting the scheduling-requested thread according to performance of a core to execute the calling thread having the same context.

Abstract translation: 包括多核处理器的片上系统的调度方法包括：检测要在多核处理器中执行的线程的调度请求，以及检测具有与调度请求线程相同上下文的调用线程， 正在多核处理器中执行的线程。 该方法包括根据核的性能重新分配或重新调度所请求的线程以执行具有相同上下文的调用线程。

公开(公告)号：US20240241451A1

公开(公告)日：2024-07-18

申请号：US18528998

申请日：2023-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daehee LEE ,  Sangwon PARK ,  Kyeonga KIM ,  Jieun PARK ,  Byeong-Hwan SON

IPC: G03F7/00 ,  G03F1/42 ,  G03F1/44 ,  H01L21/266

CPC classification number: G03F7/70633 ,  G03F1/42 ,  G03F1/44 ,  G03F7/70683 ,  H01L21/266

Abstract: A method of measuring overlay, including forming an active region on a cell region of a substrate and forming at least one overlay key structure on a scribe lane region of the substrate, forming a first mask pattern on the active region and forming a first sub-pattern on the overlay key structure, checking an alignment using the first sub-pattern, performing a first ion implantation process into the substrate, forming a second mask pattern on the active region and forming a second sub-pattern on the overlay key structure, checking the alignment using the second sub-pattern, and performing a second ion implantation process into the substrate, wherein a second width of the second sub-pattern is greater than a first width of the first sub-pattern.