公开(公告)号：US20190198511A1

公开(公告)日：2019-06-27

申请号：US16283141

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN ,  Zhiliang XIA ,  Ahn-Sik MOON ,  Se-Jun PARK ,  Joon-Sung LIM ,  Sung-Min HWANG

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11582

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.