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公开(公告)号:US20200186323A1
公开(公告)日:2020-06-11
申请号:US16274114
申请日:2019-02-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhiqiang Huang , Hiep Pham , Chih-Wei Yao
Abstract: An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.
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公开(公告)号:US10812088B2
公开(公告)日:2020-10-20
申请号:US16220898
申请日:2018-12-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhiqiang Huang , Chih-Wei Yao , Hiep Pham
IPC: H03L7/087 , H04L27/227 , H03L7/08 , H03L7/10
Abstract: A synchronized in-phase/quadrature phase (I/Q) detection circuit and a method of the same are provided. The synchronized I/Q detection circuit includes a first logic circuit; a first filter; a first reset and sampling circuit; a first multiplexer; a second logic circuit; a second filter; a second reset and sampling circuit; a signal generator; and a comparator.
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公开(公告)号:US11233627B2
公开(公告)日:2022-01-25
申请号:US17070577
申请日:2020-10-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhiqiang Huang , Hiep Pham , Chih-Wei Yao
Abstract: An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.
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公开(公告)号:US11050428B2
公开(公告)日:2021-06-29
申请号:US17010322
申请日:2020-09-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhiqiang Huang , Chih-Wei Yao , Hiep Pham
IPC: H03L7/087 , H04L27/227 , H03L7/08 , H03L7/10
Abstract: A synchronized I/Q detection circuit is provided. A first subset of input signals and, subsequently, a second subset of input signals are provided by a first multiplexer and received by a first phase detector. Outputs of the first phase detector are receiving, by a first reset and sampling circuit. A second set of input signals are provided by a second multiplexer and received by a second phase detector, from a second multiplexer, while the first multiplexer receives the first and second subsets of input signals. The first subset of input signals has a same phase order as the second set of input signals, and the second subset of input signals has a different phase order than the second set of input signals. Outputs of the second phase detector are received by a second reset and sampling circuit. A comparator outputs a detected phase difference based on the outputs of the first and second reset and sampling circuits.
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公开(公告)号:US20210028919A1
公开(公告)日:2021-01-28
申请号:US17070577
申请日:2020-10-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhiqiang Huang , Hiep Pham , Chih-Wei Yao
Abstract: An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.
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