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公开(公告)号：US20210398597A1
公开(公告)日：2021-12-23
申请号：US17462298
申请日：2021-08-31
发明人： Seungwoo SEO , Byeongho KIM , Jaehyun PARK , Jungho AHN , Minbok WI , Sunjung LEE , Eojin LEE , Wonkyung JUNG , Jongwook CHUNG , Jaewan CHOI
摘要： A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.
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公开(公告)号：US20210110876A1
公开(公告)日：2021-04-15
申请号：US16833864
申请日：2020-03-30
发明人： Seungwoo SEO , Byeongho KIM , Jaehyun PARK , Jungho AHN , Minbok WI , Sunjung LEE , Eojin LEE , Wonkyung JUNG , Jongwook CHUNG , Jaewan CHOI
摘要： A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.
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公开(公告)号：US20220374693A1
公开(公告)日：2022-11-24
申请号：US17876136
申请日：2022-07-28
发明人： Yuhwan RO , Byeongho KIM , Jaehyun PARK , Jungho AHN , Minbok WI , Sunjung LEE , Eojin LEE , Wonkyung JUNG , Jongwook CHUNG , Jaewan CHOI
摘要： A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.
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公开(公告)号：US20230138659A1
公开(公告)日：2023-05-04
申请号：US17887145
申请日：2022-08-12
发明人： Jung Ho AHN , Sunjung LEE , Hailong LI , Jaewan CHOI
IPC分类号： G06N3/04
摘要： A device and method with transformer model implementation are provided. The electronic device includes a processor configured to perform an inference by implementing a transformer model including a plurality of encoders and a plurality of decoders, and a memory configured to store instructions to be executed by the processor. Each of the encoders and the decoders includes an attention block that determines an attention value. The processor is configured to perform a first sub-softmax tile-wise operation in the attention block, perform a reduction operation to determine an adjustment factor based on a resulting value of the first sub-softmax operation, and perform a second sub-softmax tile-wise operation based on a resulting value of the reduction operation.
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公开(公告)号：US20220283984A1
公开(公告)日：2022-09-08
申请号：US17369298
申请日：2021-07-07
发明人： Dongyoung KIM , Jung Ho AHN , Sunjung LEE , Jaewan CHOI
摘要： A neural processor is provided. The neural processor includes a matrix device which is configured to generate an output feature map by processing a standard convolution operation and which has a systolic array architecture, and accelerators with an adder-tree structure which are configured to process depth-wise convolution operations for each of elements of the output feature map corresponding to lanes of the matrix device.
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