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公开(公告)号：US20220374693A1
公开(公告)日：2022-11-24
申请号：US17876136
申请日：2022-07-28
发明人： Yuhwan RO , Byeongho KIM , Jaehyun PARK , Jungho AHN , Minbok WI , Sunjung LEE , Eojin LEE , Wonkyung JUNG , Jongwook CHUNG , Jaewan CHOI
摘要： A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.
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公开(公告)号：US20240184462A1
公开(公告)日：2024-06-06
申请号：US18440461
申请日：2024-02-13
发明人： Hyunsoo KIM , Seungwon LEE , Yuhwan RO
CPC分类号： G06F3/0626 , G06F3/061 , G06F3/0629 , G06F3/0673 , G06F7/575 , G06N3/02
摘要： A method of operating a storage device includes storing received input data of a first format, converting the input data into a second format for an operation to be performed on the input data of the second format using an operator included in the storage device, and converting the input data into a second format for an operation to be performed on the input data, through an operator included in the storage device, and re-storing the input data of the second format.
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公开(公告)号：US20240257851A1
公开(公告)日：2024-08-01
申请号：US18499551
申请日：2023-11-01
发明人： Sanghoon CHA , Yuhwan RO , Seungwoo SEO
CPC分类号： G11C8/06 , G11C7/1063 , G11C8/04
摘要： A memory device includes: a memory bank module comprising a memory bank; and an operation module comprising a processing in memory (PIM) block, wherein the memory bank comprises: an array of memory cells arranged in a plurality of rows and a plurality of columns; a row buffer configured to store data of a row corresponding to a row address among the plurality of rows; and a selecting module configured to select first data and second data corresponding to a column address from among the data stored in the row buffer, wherein the first data is transmitted to the PIM block through a first data path connected between the selecting module and the PIM block, and the second data is transmitted to the PIM block through a second data path connected between the selecting module and the PIM block.
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公开(公告)号：US20240070068A1
公开(公告)日：2024-02-29
申请号：US18350074
申请日：2023-07-11
发明人： Hyunsoo KIM , Yuhwan RO
IPC分类号： G06F12/02
CPC分类号： G06F12/0292 , G06F2212/1016
摘要： Disclosed are a device and method with memory request processing using an extension of a memory address space. An electronic device includes a host processor configured to generate a memory request and a memory address that is mapped to a target memory mode that is any one of available memory modes and is mapped to a physical memory address to which the memory request is to be applied, a memory controller configured to generate the physical memory address and a command according to the target memory mode mapped to the memory address based on the memory request and the memory address received from the host processor, and a memory configured to execute, at the physical memory address, the command received from the memory controller.
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公开(公告)号：US20220292033A1
公开(公告)日：2022-09-15
申请号：US17591928
申请日：2022-02-03
发明人： Hak-soo YU , Shinhaeng KANG , Yuhwan RO
摘要： A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.
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公开(公告)号：US20220066660A1
公开(公告)日：2022-03-03
申请号：US17202591
申请日：2021-03-16
发明人： Hyunsoo KIM , Seungwon LEE , Yuhwan RO
摘要： A method of operating a storage device includes storing received input data of a first format, converting the input data into a second format for an operation to be performed on the input data of the second format using an operator included in the storage device, and converting the input data into a second format for an operation to be performed on the input data, through an operator included in the storage device, and re-storing the input data of the second format.
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公开(公告)号：US20240241828A1
公开(公告)日：2024-07-18
申请号：US18415083
申请日：2024-01-17
发明人： Yuhwan RO , Hyunsoo KIM
IPC分类号： G06F12/0815
CPC分类号： G06F12/0815
摘要： Disclosed are an electronic device for maintaining the cache coherency of data related to a processing-in-memory (PIM) operation, a processor, and an operating method of the electronic device. The electronic device includes: a processor configured to, when processing an instruction causing a processing-in-memory (PIM) operation, selectively target, for movement from a cache to a memory, data related to the PIM operation that is stored in the cache; and the memory configured to, based on the targeting of the data for movement from the cache to the memory, receive the data from the cache, and perform the PIM operation on the data in the memory based on a command corresponding to the instruction that is relayed from the processor.
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公开(公告)号：US20220107803A1
公开(公告)日：2022-04-07
申请号：US17314476
申请日：2021-05-07
发明人： Yuhwan RO , Shinhaeng KANG , Seongil O , Seungwoo SEO
IPC分类号： G06F9/30 , G06F9/50 , G06F13/16 , H03K19/173
摘要： A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.
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