公开(公告)号：US20180294017A1

公开(公告)日：2018-10-11

申请号：US15789638

申请日：2017-10-20

Applicant: SanDisk Technologies LLC

Inventor： Yingchang Chen ,  Chun-Ju Chu

IPC: G11C7/10 ,  G11C7/08 ,  G11C7/14

CPC classification number: G11C7/1051 ,  G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C7/08 ,  G11C7/106 ,  G11C7/12 ,  G11C7/14 ,  G11C29/021 ,  G11C29/028

Abstract: A sense circuit includes memory cell characterization circuitry, storage circuitry, switching circuitry, and bit line biasing circuitry. The sense circuit is configured to perform a sense operation to sense a characterization of a memory cell. During a pre-charge phase, the memory cell characterization circuitry and the bit line biasing circuitry set differential voltages in the storage circuitry to levels dependent on input offset voltages according to certain polarities. The storage circuitry maintains the differential voltages during the sense phase, allowing the memory cell characterization circuitry to cancel output the input offset voltages when generating output voltages used to identify a characterization of the memory cell. The memory cell characterization circuitry also generates its output voltage based on a reference current through a reference bit line. Doing so may allow the memory cell characterization circuitry to cancel out background noise current generated on the bit line during the sense operation.

公开(公告)号：US10319420B2

公开(公告)日：2019-06-11

申请号：US15789638

申请日：2017-10-20

Applicant: SanDisk Technologies LLC

Inventor： Yingchang Chen ,  Chun-Ju Chu

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/14 ,  G11C7/08 ,  G11C7/02 ,  G11C7/12 ,  G11C29/02

Abstract: A sense circuit includes memory cell characterization circuitry, storage circuitry, switching circuitry, and bit line biasing circuitry. The sense circuit is configured to perform a sense operation to sense a characterization of a memory cell. During a pre-charge phase, the memory cell characterization circuitry and the bit line biasing circuitry set differential voltages in the storage circuitry to levels dependent on input offset voltages according to certain polarities. The storage circuitry maintains the differential voltages during the sense phase, allowing the memory cell characterization circuitry to cancel output the input offset voltages when generating output voltages used to identify a characterization of the memory cell. The memory cell characterization circuitry also generates its output voltage based on a reference current through a reference bit line. Doing so may allow the memory cell characterization circuitry to cancel out background noise current generated on the bit line during the sense operation.