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Patent Agency Ranking
公开(公告)号：US20210373085A1
公开(公告)日：2021-12-02
申请号：US16883718
申请日：2020-05-26
Applicant: SanDisk Technologies LLC
Inventor： Dat Tran , Loc Tu , Kirubakaran Periyannan , Nyi Nyi Thein
Abstract: Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path connected to a first pin and a parallel second path connected to a second pin. A comparator is connected to the output path of the current mirror. By controlling the on and off states of transistors in the first and second paths, and evaluating the voltage of the output path, the short circuits can be detected.
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公开(公告)号：US11372056B2
公开(公告)日：2022-06-28
申请号：US16883718
申请日：2020-05-26
Applicant: SanDisk Technologies LLC
Inventor： Dat Tran , Loc Tu , Kirubakaran Periyannan , Nyi Nyi Thein
Abstract: Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path connected to a first pin and a parallel second path connected to a second pin. A comparator is connected to the output path of the current mirror. By controlling the on and off states of transistors in the first and second paths, and evaluating the voltage of the output path, the short circuits can be detected.
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公开(公告)号：US10984883B1
公开(公告)日：2021-04-20
申请号：US16728447
申请日：2019-12-27
Applicant: SanDisk Technologies LLC
Inventor： Sowjanya Tungala , Sini Balakrishnan , Sowjanya Sunkavelli , Sridhar Yadala , Dat Tran , Loc Tu , Kirubakaran Periyannan
Abstract: A memory management method includes identifying memory segments of a memory device. The method also includes identifying, for each memory segment, a number of faulty columns and determining a total number of faulty columns for the memory device. The method also includes, in response to a determination that the total number of faulty columns is greater than a threshold, identifying a memory segment having a highest number of faulty columns. The method also includes disabling the memory segment. Another method includes identifying, for each memory segment, a number of faulty memory blocks and determining a total number of faulty memory blocks. The method also includes, in response to a determination that the total number of faulty memory blocks is greater than a threshold, identifying a memory segment having a highest number of faulty memory blocks. The method also includes disabling the memory segment.
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公开(公告)号：US11086539B2
公开(公告)日：2021-08-10
申请号：US16659353
申请日：2019-10-21
Applicant: SanDisk Technologies LLC
Inventor： Dat Tran , Loc Tu , Kirubakaran Periyannan
IPC: G06F3/06
Abstract: Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.
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公开(公告)号：US20210117086A1
公开(公告)日：2021-04-22
申请号：US16659353
申请日：2019-10-21
Applicant: SanDisk Technologies LLC
Inventor： Dat Tran , Loc Tu , Kirubakaran Periyannan
IPC: G06F3/06
Abstract: Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.
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