公开(公告)号：US20240184667A1

公开(公告)日：2024-06-06

申请号：US18350350

申请日：2023-07-11

Applicant: SanDisk Technologies LLC

Inventor： SAJAL MITTAL ,  Siddhesh Darne

IPC: G06F11/10

CPC classification number: G06F11/1008

Abstract: A circuit for detecting an error in a byte of data transmitted over a channel includes a controller having a first DBI encoder configured to perform a first DBI encoding on a received byte of data. The circuit also includes a channel configured to receive the encoded byte from the controller. The circuit also includes a non-volatile memory having a second DBI encoder and configured to (1) perform a second DBI encoding on the encoded byte received over the channel, (2) check a DBI flag for the byte after the second DBI encoding, and (3) determine that the byte of data contains an error when the DBI flag after the second DBI encoding is 1. If the byte contains an error then it can be concluded that the channel contains a defect. In case of an error a write operation to memory core can be stopped.

公开(公告)号：US20230343377A1

公开(公告)日：2023-10-26

申请号：US17725441

申请日：2022-04-20

Applicant: SanDisk Technologies LLC

Inventor： SAJAL MITTAL ,  SNEHA BHATIA

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1012 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1039

Abstract: A data path architecture and corresponding method of operation are disclosed that permit a first-in-first out (FIFO) buffer to immediately flush data—including potentially invalid initial byte(s)—upon receipt of a high-speed clock signal, and according to which, a delay difference between a data path clock signal and a high-speed clock signal is compensated for at a controller side by, for example, adjusting RE latency to discard/ignore the initially invalid bytes rather than by modifying FIFO depth or varying a number of delay stages in the high-speed clock signal path in order to satisfy the FIFO depth. Because FIFO depth is not used to absorb the clock signal delay difference, there is no need to modify the architecture (e.g., change the depth of a FIFO) to accommodate variation in the clock signal delay difference across different products/product generations, thereby providing high scalability.