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公开(公告)号:US20230343377A1
公开(公告)日:2023-10-26
申请号:US17725441
申请日:2022-04-20
发明人: SAJAL MITTAL , SNEHA BHATIA
CPC分类号: G11C7/222 , G11C7/1012 , G11C7/1057 , G11C7/1084 , G11C7/1039
摘要: A data path architecture and corresponding method of operation are disclosed that permit a first-in-first out (FIFO) buffer to immediately flush data—including potentially invalid initial byte(s)—upon receipt of a high-speed clock signal, and according to which, a delay difference between a data path clock signal and a high-speed clock signal is compensated for at a controller side by, for example, adjusting RE latency to discard/ignore the initially invalid bytes rather than by modifying FIFO depth or varying a number of delay stages in the high-speed clock signal path in order to satisfy the FIFO depth. Because FIFO depth is not used to absorb the clock signal delay difference, there is no need to modify the architecture (e.g., change the depth of a FIFO) to accommodate variation in the clock signal delay difference across different products/product generations, thereby providing high scalability.
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公开(公告)号:US20230395108A1
公开(公告)日:2023-12-07
申请号:US17832479
申请日:2022-06-03
CPC分类号: G11C7/222 , G11C7/109 , G11C7/1063 , G11C7/1039
摘要: Systems and methods disclosed herein provide for selectively activating or deactivating one or more memory of a memory array, such that related data path logic of deactivated memory dies neither detects nor processes control signals or data signals for data operations. Examples of the systems and methods provided herein operate to detect a first enable signal at a memory die and detect a first data signal on input/output (I/O) receivers of the memory die. Responsive to detecting at least the first enable signal, a bit value encoded in the first data signal is latched to obtain a first bit pattern. A second bit pattern is obtained, and, based on a comparison of the first bit pattern to the second bit pattern, the I/O receivers of the memory die are activated.
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