公开(公告)号：US09595338B2

公开(公告)日：2017-03-14

申请号：US14495283

申请日：2014-09-24

申请人： SanDisk Technologies LLC

发明人： Juan Carlos Lee ,  Hao Nguyen ,  Man Mui ,  Tien-chien Kuo ,  Yuki Mizutani

IPC分类号： G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G11C16/14 ,  G11C7/12 ,  G11C7/14

CPC分类号： G11C16/24 ,  G11C7/12 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26

摘要： In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.

摘要翻译： 在NAND闪存中，位线预充/放电时间可以是确定程序，擦除和读取性能的主要组成部分。 在常规布置中，位线电平由感测放大器设置，位线通过读出放大器路径被放电到源极线电平。 在这种布置下，基于位线的RC常数，预充电/放电时间由远端（相对于感测放大器）支配。 因此，减少位线预充电/放电时间，从而提高了NAND​​闪存的性能，从而提高了整体系统的性能。 为了解决这个问题，通过使用虚拟NAND串将额外的路径引入到公共源级别的位线之间。 在基于示例性的基于3D-NAND（BiCS）的实施例中，虚拟NAND串从虚拟块中获取，其中虚拟块可以被放置在整个阵列中以均匀分布放电电流。