公开(公告)号：US20060197847A1

公开(公告)日：2006-09-07

申请号：US11415000

申请日：2006-05-01

申请人： Sandra Johnson ,  Shih-Chung Chao ,  Nadi Itani ,  Caiyi Wang ,  Brannon Harris ,  Ash Prabala ,  Douglas Holberg ,  Alan Hansford ,  Syed Azim ,  David Welland

发明人： Sandra Johnson ,  Shih-Chung Chao ,  Nadi Itani ,  Caiyi Wang ,  Brannon Harris ,  Ash Prabala ,  Douglas Holberg ,  Alan Hansford ,  Syed Azim ,  David Welland

IPC分类号： H04N5/235

CPC分类号： H04N5/3575 ,  H04N5/335 ,  H04N5/361

摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

公开(公告)号：US07289145B2

公开(公告)日：2007-10-30

申请号：US11415000

申请日：2006-05-01

申请人： Sandra Marie Johnson ,  Shih-Chung Chao ,  Nadi Rafik Itani ,  Caiyi Wang ,  Brannon Craig Harris ,  Ash Prabala ,  Douglas R. Holberg ,  Alan Hansford ,  Syed Khalid Azim ,  David R. Welland

发明人： Sandra Marie Johnson ,  Shih-Chung Chao ,  Nadi Rafik Itani ,  Caiyi Wang ,  Brannon Craig Harris ,  Ash Prabala ,  Douglas R. Holberg ,  Alan Hansford ,  Syed Khalid Azim ,  David R. Welland

IPC分类号： H04N5/235

CPC分类号： H04N5/3575 ,  H04N5/335 ,  H04N5/361

摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括用于从CCD系统接收数据的相关双样本和可变增益（CDSVGA）电路以及首先通过调整来控制增益的自动增益控制（AGC）电路 所述CCD系统然后为了更高的增益水平，使得所述CDSVGA电路和数字增益电路中的增益调整产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路。 处理电路包括模拟前端和数字信号处理系统，用于捕获全运动视频并输出CCIR 601 4：2：2 YCrCb视频数据输出以便呈现在用户选择的显示器上。