公开(公告)号：US20120275239A1

公开(公告)日：2012-11-01

申请号：US13219624

申请日：2011-08-27

申请人： Sang Hyun SONG

发明人： Sang Hyun SONG

IPC分类号： G11C7/10

CPC分类号： G11C11/40607 ,  G11C16/26

摘要： A memory apparatus includes a memory cell array comprising a plurality of memory cells connected with a plurality of bit lines and a plurality of word lines, a page buffer unit connected to the plurality of bit lines and latch data read from a memory cell selected from the plurality of memory cells, and a control unit configured to generate a refresh signal according to a prestored current status and provide the refresh signal to the page buffer unit in order to substantially prevent loss of the data latched by the page buffer unit.

摘要翻译： 存储器装置包括存储单元阵列，该存储单元阵列包括与多个位线连接的多个存储单元和多个字线，连接到多个位线的页缓冲器单元以及从存储单元读取的锁存数据 多个存储单元，以及控制单元，被配置为根据预存的当前状态生成刷新信号，并将刷新信号提供给页缓冲器单元，以便基本上防止由页缓冲器单元锁存的数据的丢失。

公开(公告)号：US20110161567A1

公开(公告)日：2011-06-30

申请号：US12839364

申请日：2010-07-19

申请人： Sang Hyun SONG

发明人： Sang Hyun SONG

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7208

摘要： A non-volatile memory device includes: first and second planes each comprising a plurality of non-volatile memory cells; first and second buffer corresponding to the first and second planes, respectively; an input/output control unit configured to selectively control input/output paths of data stored in the first and second page buffers; a flash interface connected to the input/output control unit; and a host connected to the flash interface.

摘要翻译： 非易失性存储器件包括：第一和第二平面，每个平面包括多个非易失性存储器单元; 第一和第二缓冲器分别对应于第一和第二平面; 输入/输出控制单元，被配置为选择性地控制存储在第一和第二页缓冲器中的数据的输入/输出路径; 连接到输入/输出控制单元的闪存接口; 和连接到闪存接口的主机。

公开(公告)号：US20130107647A1

公开(公告)日：2013-05-02

申请号：US13601609

申请日：2012-08-31

申请人： Tai Kyu KANG ,  Sang Hyun SONG

发明人： Tai Kyu KANG ,  Sang Hyun SONG

IPC分类号： G11C7/00

CPC分类号： G11C16/225 ,  G11C16/06 ,  G11C16/32

摘要： The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and outputting ROM data corresponding to a selected algorithm, a program counter for outputting a ROM address to the ROM so as to sequentially operate the selected algorithm, an internal circuit for performing an operation corresponding to the selected algorithm in response to a plurality of internal circuit control signals in response to the ROM data, and a reset circuit for stopping progress of a running algorithm by initializing the program counter in response to a reset command input from an outside, and performing the reset algorithm.

摘要翻译： 本公开涉及半导体器件和操作半导体器件的方法。 半导体器件包括用于存储程序算法的ROM，擦除算法，读取算法和复位算法，并且输出与所选择的算法相对应的ROM数据，用于向ROM输出ROM地址以便顺序操作的程序计数器 所选择的算法，响应于ROM数据而响应于多个内部电路控制信号执行与所选算法对应的操作的内部电路，以及用于通过初始化程序计数器来停止运行算法的进展的复位电路 响应于从外部输入的复位命令，并执行复位算法。