公开(公告)号：US20070208902A1

公开(公告)日：2007-09-06

申请号：US11614877

申请日：2006-12-21

申请人： Sang-Kyun Park ,  Il-Man Bae ,  Han-Gu Sohn ,  Yun-Hee Shin

发明人： Sang-Kyun Park ,  Il-Man Bae ,  Han-Gu Sohn ,  Yun-Hee Shin

IPC分类号： G06F12/00

CPC分类号： G11C7/1075 ,  G11C5/025 ,  G11C7/1048 ,  G11C11/4093

摘要： A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.

摘要翻译： 多处理器系统包括耦合到第一总线的第一处理器，耦合到第二总线的第二处理器，耦合到第一总线和第二总线的第一存储器以及耦合到第二总线的第二存储器。 第一处理器被配置为通过第一总线访问第一存储器，并且第二处理器被配置为通过第二总线访问第一存储器和第二存储器。

公开(公告)号：US07984261B2

公开(公告)日：2011-07-19

申请号：US11614877

申请日：2006-12-21

申请人： Sang-Kyun Park ,  Il-Man Bae ,  Han-Gu Sohn ,  Yun-Hee Shin

发明人： Sang-Kyun Park ,  Il-Man Bae ,  Han-Gu Sohn ,  Yun-Hee Shin

IPC分类号： G06F12/00

CPC分类号： G11C7/1075 ,  G11C5/025 ,  G11C7/1048 ,  G11C11/4093

摘要： A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.

摘要翻译： 多处理器系统包括耦合到第一总线的第一处理器，耦合到第二总线的第二处理器，耦合到第一总线和第二总线的第一存储器以及耦合到第二总线的第二存储器。 第一处理器被配置为通过第一总线访问第一存储器，并且第二处理器被配置为通过第二总线访问第一存储器和第二存储器。

公开(公告)号：US07870326B2

公开(公告)日：2011-01-11

申请号：US11819601

申请日：2007-06-28

申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

IPC分类号： G06F12/00

CPC分类号： G06F12/02

摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

摘要翻译： 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的 通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址， 通过第二个端口，银行地址选择第四个存储器，作为与银行地址相同的银行地址，选择第三个存储器 银行通过第一个港口。

公开(公告)号：US20110107006A1

公开(公告)日：2011-05-05

申请号：US12929222

申请日：2011-01-10

申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

IPC分类号： G06F12/00

CPC分类号： G06F12/02

摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

公开(公告)号：US20080172516A1

公开(公告)日：2008-07-17

申请号：US11819601

申请日：2007-06-28

申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

IPC分类号： G06F12/02

CPC分类号： G06F12/02

摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

摘要翻译： 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的 通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址， 通过第二个端口，银行地址选择第四个存储器，作为银行地址作为银行地址，选择第三个存储器 银行通过第一个港口。

公开(公告)号：US07941612B2

公开(公告)日：2011-05-10

申请号：US11829859

申请日：2007-07-27

申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

IPC分类号： G06F12/00

CPC分类号： G11C7/1075 ,  G11C7/1012 ,  G11C11/4096

摘要： A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

摘要翻译： 多路可及半导体存储器件提供处理器之间的接口功能。 存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径 响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。