公开(公告)号：US07984261B2

公开(公告)日：2011-07-19

申请号：US11614877

申请日：2006-12-21

申请人： Sang-Kyun Park ,  Il-Man Bae ,  Han-Gu Sohn ,  Yun-Hee Shin

发明人： Sang-Kyun Park ,  Il-Man Bae ,  Han-Gu Sohn ,  Yun-Hee Shin

IPC分类号： G06F12/00

CPC分类号： G11C7/1075 ,  G11C5/025 ,  G11C7/1048 ,  G11C11/4093

摘要： A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.

摘要翻译： 多处理器系统包括耦合到第一总线的第一处理器，耦合到第二总线的第二处理器，耦合到第一总线和第二总线的第一存储器以及耦合到第二总线的第二存储器。 第一处理器被配置为通过第一总线访问第一存储器，并且第二处理器被配置为通过第二总线访问第一存储器和第二存储器。

公开(公告)号：US20070208902A1

公开(公告)日：2007-09-06

申请号：US11614877

申请日：2006-12-21

申请人： Sang-Kyun Park ,  Il-Man Bae ,  Han-Gu Sohn ,  Yun-Hee Shin

发明人： Sang-Kyun Park ,  Il-Man Bae ,  Han-Gu Sohn ,  Yun-Hee Shin

IPC分类号： G06F12/00

CPC分类号： G11C7/1075 ,  G11C5/025 ,  G11C7/1048 ,  G11C11/4093

摘要： A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.

摘要翻译： 多处理器系统包括耦合到第一总线的第一处理器，耦合到第二总线的第二处理器，耦合到第一总线和第二总线的第一存储器以及耦合到第二总线的第二存储器。 第一处理器被配置为通过第一总线访问第一存储器，并且第二处理器被配置为通过第二总线访问第一存储器和第二存储器。

公开(公告)号：US20110107006A1

公开(公告)日：2011-05-05

申请号：US12929222

申请日：2011-01-10

申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

IPC分类号： G06F12/00

CPC分类号： G06F12/02

摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

公开(公告)号：US07941612B2

公开(公告)日：2011-05-10

申请号：US11829859

申请日：2007-07-27

申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

IPC分类号： G06F12/00

CPC分类号： G11C7/1075 ,  G11C7/1012 ,  G11C11/4096

摘要： A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

摘要翻译： 多路可及半导体存储器件提供处理器之间的接口功能。 存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径 响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

公开(公告)号：US20080172516A1

公开(公告)日：2008-07-17

申请号：US11819601

申请日：2007-06-28

申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

IPC分类号： G06F12/02

CPC分类号： G06F12/02

摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

摘要翻译： 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的 通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址， 通过第二个端口，银行地址选择第四个存储器，作为银行地址作为银行地址，选择第三个存储器 银行通过第一个港口。

公开(公告)号：US07870326B2

公开(公告)日：2011-01-11

申请号：US11819601

申请日：2007-06-28

申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

IPC分类号： G06F12/00

CPC分类号： G06F12/02

摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

摘要翻译： 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的 通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址， 通过第二个端口，银行地址选择第四个存储器，作为与银行地址相同的银行地址，选择第三个存储器 银行通过第一个港口。

公开(公告)号：US07791964B2

公开(公告)日：2010-09-07

申请号：US12044174

申请日：2008-03-07

申请人： Young-Min Lee ,  Han-Gu Sohn

发明人： Young-Min Lee ,  Han-Gu Sohn

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1072

摘要： A memory system and related method of operation are disclosed. The memory system includes a memory configured to generate a data strobe signal including “(n/2)+1” clock signals, where “n” is a number of base data blocks in read data synchronously transferred by the memory during a read operation, and a memory controller configured to receive the read data, receive the data strobe signal, delay the data strobe signal to generate a delayed data strobe signal, and synchronously output “n/2” sampled data blocks to a requesting device in relation to the delayed data strobe signal.

摘要翻译： 公开了一种存储系统及其相关操作方法。 存储器系统包括被配置为产生包括“（n / 2）+1”个时钟信号的数据选通信号的存储器，其中“n”是在读取操作期间由存储器同步传送的读取数据中的基本数据块的数量， 以及存储器控制器，被配置为接收所读取的数据，接收数据选通信号，延迟数据选通信号以产生延迟的数据选通信号，并且相对于所延迟的数据选通信号同步地将“n / 2”个采样数据块输出到请求设备 数据选通信号。

公开(公告)号：US20090024803A1

公开(公告)日：2009-01-22

申请号：US12216188

申请日：2008-07-01

申请人： Jin-Hyoung Kwon ,  Han-Gu Sohn

发明人： Jin-Hyoung Kwon ,  Han-Gu Sohn

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0638 ,  G06F2212/206

摘要： A semiconductor memory device for use in a multiprocessor system may be provided. A chip size may be controlled, and a design of circuit may be relatively simplified. The semiconductor memory device for use in a multiprocessor system may include at least two shared memory areas commonly accessible by processors of the multiprocessor system through different ports and assigned with a predetermined memory capacity unit to a portion of a memory cell array, a single shared register adapted outside the memory cell array, corresponding to disable areas formed within the shared memory areas, and/or a switching unit for connecting a decoder of a selected shared memory area to the shared register in response to an applied control signal, to match the shared register to the disable area of the selected shared memory area. A shared register may be commonly used in corresponding to a plurality of shared memory areas, thereby reducing or preventing a chip size increase and simplifying a design of the circuit.

摘要翻译： 可以提供用于多处理器系统的半导体存储器件。 可以控制芯片尺寸，并且可以相对简化电路的设计。 在多处理器系统中使用的半导体存储器件可以包括通过不同端口通常可由多处理器系统的处理器访问的至少两个共享存储器区域，并且向存储器单元阵列的一部分分配预定的存储器容量单元，单个共享寄存器 对应于形成在共享存储器区域内的禁用区域，和/或用于响应于所施加的控制信号将所选择的共享存储器区域的解码器连接到共享寄存器的切换单元，以匹配共享存储器单元阵列 注册到所选共享内存区域的禁用区域。 可以在多个共享存储区域中共同使用共享寄存器，从而减少或防止芯片尺寸增加并简化电路的设计。

公开(公告)号：US20080313418A1

公开(公告)日：2008-12-18

申请号：US12140428

申请日：2008-06-17

申请人： Jin-Hyoung KWON ,  Han-Gu Sohn

发明人： Jin-Hyoung KWON ,  Han-Gu Sohn

IPC分类号： G06F12/00

CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C7/1075 ,  G11C7/22

摘要： A semiconductor memory device for use in a multiprocessor system includes a shared memory area and a reset signal generator. The shared memory area is accessible by the processors of the multiprocessor system through different ports, and is assigned to a portion of a memory cell array. The reset signal generator is configured to provide a reset enable signal to a processor, predetermined as a slave processor among the multiple processors, for a predetermined time after an initial booting of the multiprocessor system. The reset signal generator also provides a reset disable signal to the slave processor after the predetermined time lapses.

摘要翻译： 用于多处理器系统的半导体存储器件包括共享存储区域和复位信号发生器。 共享存储器区域可由多处理器系统的处理器通过不同端口访问，并被分配给存储单元阵列的一部分。 复位信号发生器被配置为在多处理器系统的初始引导之后的预定时间内向处理器提供复位使能信号，预定为多个处理器中的从属处理器。 复位信号发生器还在经过预定时间之后向从属处理器提供复位禁止信号。

公开(公告)号：US07269085B2

公开(公告)日：2007-09-11

申请号：US11317429

申请日：2005-12-23

申请人： Han-Gu Sohn ,  Sei-Jin Kim

发明人： Han-Gu Sohn ,  Sei-Jin Kim

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4061

摘要： A semiconductor device is provided. The semiconductor device includes a storage part storing an address for weak cells in a nonvolatile state; and a dynamic semiconductor memory device including: a memory cell array having normal cells and the weak cells to be refreshed; and a refresh control part performing a refresh operation for the weak cells, wherein a refresh period for the weak cells is shorter than a refresh period for the normal cells when the address applied in a refresh operation mode coincides with the address stored in the storage part.

摘要翻译： 提供半导体器件。 半导体器件包括：存储非易失性状态的弱电池的地址的存储部; 以及动态半导体存储器件，包括：具有正常单元的存储单元阵列和要刷新的弱单元; 以及对所述弱小区执行刷新操作的刷新控制部分，其中当刷新操作模式中应用的地址与存储在存储部分中的地址一致时，所述弱小区的刷新周期短于正常小区的刷新周期 。