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    LATENCY CIRCUIT USING DIVISION METHOD RELATED TO CAS LATENCY AND SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    LATENCY CIRCUIT USING DIVISION METHOD RELATED TO CAS LATENCY AND SEMICONDUCTOR MEMORY DEVICE 有权
    使用与CAS LATENCY和SEMICONDUCTOR MEMORY DEVICE相关的部分方法的延迟电路

    公开(公告)号：US20100128543A1

    公开(公告)日：2010-05-27

    申请号：US12697547

    申请日：2010-02-01

    申请人： Sang-hyuk KWON ,  Byung-hoon JEONG

    发明人： Sang-hyuk KWON ,  Byung-hoon JEONG

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2. The latency circuit also includes a latency signal generator generating a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command.

    摘要翻译： 用于半导体存储器件的等待时间电路包括等待时间控制时钟发生器，其产生来自外部时钟的m分割除法信号和来自m分割除法信号的至少一个等待时间控制时钟，其中m是大于 等待时间电路还包括响应于至少一个等待时间控制时钟产生等待时间信号的等待时间信号发生器，等待时间控制信号和内部读取命令信号，其中等待时间控制信号是从列产生的 地址选通（CAS）延迟和内部读命令信号是响应于接收到的读命令产生的。