Method of and Apparatus for Making a Three-Dimensional Object
    1.
    发明申请
    Method of and Apparatus for Making a Three-Dimensional Object 有权
    制作三维物体的方法和装置

    公开(公告)号:US20120139166A1

    公开(公告)日:2012-06-07

    申请号:US13274847

    申请日:2011-10-17

    Abstract: An apparatus for making a three-dimensional object includes a table, a powdery layer-former that forms a powdery layer on the table, and an optical beam-irradiator that irradiates an optical beam on a predetermined region of the powdery layer to sinter the predetermined region of the powdery layer. A chamber for accommodating the table and the powdery layer-former and a lid for opening and closing an opening defined in the chamber at a location immediately above an optical beam-irradiating range are provided. The three-dimensional object is taken out from the chamber through the opening upon completion of the sintering, and the optical beam-irradiator is disposed at a position deviated from immediately above the optical beam-irradiating range to obliquely irradiate the optical beam on the powdery layer.

    Abstract translation: 一种用于制造三维物体的装置包括:桌子,在桌子上形成粉末层的粉末层形成剂;以及光束照射器,其将光束照射在粉末层的预定区域上以烧结预定的 粉末层的区域。 提供了一种用于容纳桌子和粉末成层剂的室,以及用于在紧邻光束照射范围的位置处开启和关闭限定在室中的开口的盖。 在完成烧结之后,三维物体通过开口从室中取出,并且光束照射器设置在偏离光束照射范围之上的位置,以将光束倾斜地照射在粉末状 层。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号:US20090045521A1

    公开(公告)日:2009-02-19

    申请号:US12188881

    申请日:2008-08-08

    Applicant: Satoshi ABE

    Inventor: Satoshi ABE

    CPC classification number: H01L23/5226 H01L23/528 H01L2924/0002 H01L2924/00

    Abstract: A semiconductor device includes: an interlayer insulation film; a lower interconnection layer; an upper interconnection layer; and a via hole extending through the interlayer insulation film to establish electric connection between the lower and upper interconnections; wherein a plurality of interconnection lines is provided in the lower interconnection layer, and a contact region is formed for contact with the via hole by partially joining at least two interconnection lines, and a void exists in a first region of the interlayer insulation film located between adjacent interconnection lines, and no void exists in a second region of the interlayer insulation film located between a contacting portion of the via hole in the contact region and an interconnection line adjacent to the contact region, whereby reliably preventing any contact between a via hole and a void formed in an interlayer insulation film even when the via hole is greatly displaced.

    Abstract translation: 半导体器件包括:层间绝缘膜; 下互连层; 上互连层; 以及延伸穿过层间绝缘膜的通孔,以在下互连和上互连之间建立电连接; 其中在所述下互连层中设置多个互连线,并且通过部分地接合至少两个互连线而形成与所述通孔相接触的接触区域,并且位于所述层间绝缘膜的位于 相邻的互连线,并且位于接触区域中的通孔的接触部分和与接触区域相邻的互连线之间的层间绝缘膜的第二区域中不存在空隙,从而可靠地防止通孔和 即使当通孔大大移位时也形成在层间绝缘膜中的空隙。

Patent Agency Ranking