公开(公告)号：US10298343B2

公开(公告)日：2019-05-21

申请号：US15448812

申请日：2017-03-03

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： David J. Dolezilek ,  Jorge Fernando Calero ,  Amandeep Singh Kalra ,  Brian T. Waldron

IPC: H04J3/06 ,  H04L12/28

Abstract: The present disclosure pertains to systems and methods for publishing time-synchronized information. In one embodiment, a system may include a time interface configured to receive a common time signal and a network interface configured to transmit a plurality of data packets using a network. A publishing subsystem may be configured to cause the system to publish at least one data value according to a schedule and the common time signal. A processing sequence number subsystem may be configured to generate a processing sequence number to be included in the plurality of data packets and to reset the processing sequence number at a fixed interval based on the common time signal. A data packet subsystem may be configured to generate a plurality of data packets comprising a respective processing sequence number and the at least one data value.

公开(公告)号：US20180254994A1

公开(公告)日：2018-09-06

申请号：US15448812

申请日：2017-03-03

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： David J. Dolezilek ,  Jorge Fernando Calero ,  Amandeep Singh Kalra ,  Brian T. Waldron

IPC: H04L12/863 ,  H04L29/08 ,  H04J3/06

CPC classification number: H04J3/0658 ,  H04L12/2816

Abstract: The present disclosure pertains to systems and methods for publishing time-synchronized information. In one embodiment, a system may include a time interface configured to receive a common time signal and a network interface configured to transmit a plurality of data packets using a network. A publishing subsystem may be configured to cause the system to publish at least one data value according to a schedule and the common time signal. A processing sequence number subsystem may be configured to generate a processing sequence number to be included in the plurality of data packets and to reset the processing sequence number at a fixed interval based on the common time signal. A data packet subsystem may be configured to generate a plurality of data packets comprising a respective processing sequence number and the at least one data value.

公开(公告)号：US20190207694A1

公开(公告)日：2019-07-04

申请号：US16294524

申请日：2019-03-06

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： David J. Dolezilek ,  Jorge Fernando Calero ,  Amandeep Singh Kalra ,  Brian T. Waldron

IPC: H04J3/06 ,  H04L12/28

CPC classification number: H04J3/0658 ,  H02H7/261 ,  H04L12/2816

Abstract: The present disclosure pertains to systems and methods for publishing time-synchronized information. In one embodiment, a system may include a time interface configured to receive a common time signal and a network interface configured to transmit a plurality of data packets using a network. A publishing subsystem may be configured to cause the system to publish at least one data value according to a schedule and the common time signal. A processing sequence number subsystem may be configured to generate a processing sequence number to be included in the plurality of data packets and to reset the processing sequence number at a fixed interval based on the common time signal. A data packet subsystem may be configured to generate a plurality of data packets comprising a respective processing sequence number and the at least one data value.