公开(公告)号：US20080140987A1

公开(公告)日：2008-06-12

申请号：US11953028

申请日：2007-12-08

申请人： Scott Rixner ,  Kartik Mohanram ,  Mihir R. Choudhury

发明人： Scott Rixner ,  Kartik Mohanram ,  Mihir R. Choudhury

IPC分类号： G06F12/06

CPC分类号： H03M13/03 ,  H03M13/033 ,  H03M13/13

摘要： A system and method for context-independent coding using frequency-based mapping schemes, sequence-based mapping schemes, memory trace-based mapping schemes, and/or transition statistics-based mapping schemes in order to reduce off-chip interconnect power consumption. State-of-the-art context-dependent, double-ended codes for processor-SDRAM off-chip interfaces require the transmitter and receiver (memory controller and SDRAM) to collaborate using the current and previously transmitted values to encode and decode data. In contrast, the memory controller can use a context-independent code to encode data stored in SDRAM and subsequently decode that data when it is retrieved, allowing the use of commodity memories. A single-ended, context-independent code is realized by assigning limited-weight codes using a frequency-based mapping technique. Experimental results show that such a code can reduce the power consumption of an uncoded off-chip interconnect by an average of 30% with less than a 0.1% degradation in performance

摘要翻译： 一种使用基于频率的映射方案，基于序列的映射方案，基于存储器跟踪的映射方案和/或基于过渡统计的映射方案的上下文无关编码的系统和方法，以便减少片外互连功耗。 处理器 - SDRAM片外接口的最先进的上下文相关的双端代码要求发送器和接收器（存储器控制器和SDRAM）使用当前和先前传输的值进行协作，以对数据进行编码和解码。 相比之下，存储器控制器可以使用与上下文无关的代码对存储在SDRAM中的数据进行编码，并随后在该数据被检索时解码该数据，从而允许使用商品存储器。 通过使用基于频率的映射技术分配有限权重码来实现单端，上下文无关代码。 实验结果表明，这样的代码可以将未编码的片外互连的功耗降低30％，平均降低0.1％，降低性能

公开(公告)号：US07979666B2

公开(公告)日：2011-07-12

申请号：US11953028

申请日：2007-12-08

申请人： Scott Rixner ,  Kartik Mohanram ,  Mihir R. Choudhury

发明人： Scott Rixner ,  Kartik Mohanram ,  Mihir R. Choudhury

IPC分类号： G06F13/00

CPC分类号： H03M13/03 ,  H03M13/033 ,  H03M13/13

摘要： A system and method for context-independent coding using frequency-based mapping schemes, sequence-based mapping schemes, memory trace-based mapping schemes, and/or transition statistics-based mapping schemes in order to reduce off-chip interconnect power consumption. State-of-the-art context-dependent, double-ended codes for processor-SDRAM off-chip interfaces require the transmitter and receiver (memory controller and SDRAM) to collaborate using the current and previously transmitted values to encode and decode data. In contrast, the memory controller can use a context-independent code to encode data stored in SDRAM and subsequently decode that data when it is retrieved, allowing the use of commodity memories. A single-ended, context-independent code is realized by assigning limited-weight codes using a frequency-based mapping technique. Experimental results show that such a code can reduce the power consumption of an uncoded off-chip interconnect by an average of 30% with less than a 0.1% degradation in performance.

摘要翻译： 一种使用基于频率的映射方案，基于序列的映射方案，基于存储器跟踪的映射方案和/或基于过渡统计的映射方案的上下文无关编码的系统和方法，以便减少片外互连功耗。 处理器 - SDRAM片外接口的最先进的上下文相关的双端代码要求发送器和接收器（存储器控制器和SDRAM）使用当前和先前传输的值进行协作，以对数据进行编码和解码。 相比之下，存储器控制器可以使用与上下文无关的代码对存储在SDRAM中的数据进行编码，并随后在该数据被检索时解码该数据，从而允许使用商品存储器。 通过使用基于频率的映射技术分配有限权重码来实现单端，上下文无关代码。 实验结果表明，这样的代码可以将未编码的片外互连的功耗降低30％，平均性能降低0.1％。

公开(公告)号：US08902672B2

公开(公告)日：2014-12-02

申请号：US13732372

申请日：2013-01-01

申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian ,  Kartik Mohanram

发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian ,  Kartik Mohanram

IPC分类号： G11C8/16 ,  G11C11/419 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C11/419 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  G11C11/412

摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.

摘要翻译： 大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据。 为了处理多个内存用户，提出了一种高效的双端口六晶体管（6T）SRAM存储单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立访问SRAM单元的真实面和假面。 单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个读取。 可以更快地处理写入操作，使得可以使用时分复用在单个周期中处理两个写入操作。 为了进一步提高双端口6T SRAM单元的运行，采用了多种算法技术来改善存储系统的运行。