公开(公告)号：US09274586B2

公开(公告)日：2016-03-01

申请号：US11222387

申请日：2005-09-07

申请人： Sundar Iyer ,  Nick McKeown ,  Morgan Littlewood

发明人： Sundar Iyer ,  Nick McKeown ,  Morgan Littlewood

IPC分类号： G06F12/00 ,  G06F1/32 ,  H04L12/861 ,  H04L12/935

CPC分类号： G06F1/3209 ,  H04L49/3009 ,  H04L49/3036 ,  H04L49/90

摘要： Many computer processing tasks require large numbers of memory intensive operations to be performed very rapidly. For example, computer network requires that packets be placed into and removed from First-In First-Out (FIFO) queues, numerous counters to be maintained and routing table look-ups to be performed. All of these operations must be performed at very high-speeds in order to keep up with today's high-speed computer network traffic. To help perform these high-speed memory tasks, a high-speed intelligent memory subsystem has been developed. The high-speed intelligent memory subsystem handles the intricacies of these memory operations such that a main process is relieved of some of its duties. Various different high-level memory interfaces for interfacing with the intelligent memory subsystem. The memory interfaces may be hardware-based or software-based. In one embodiment, two layers of interfaces are implemented such that an internal interface may evolve over successive generations without affecting an externally visible interface.

摘要翻译： 许多计算机处理任务需要非常快速地执行大量的内存密集型操作。 例如，计算机网络要求将数据包放入先入先出（FIFO）队列中的数据包，要保留的许多计数器和要执行的路由表查找。 所有这些操作必须以非常高的速度执行，以便跟上当今的高速计算机网络流量。 为了帮助执行这些高速存储器任务，开发了高速智能存储器子系统。 高速智能存储器子系统处理这些记忆操作的复杂性，使得主程序免除了其一些职责。 各种不同的高级存储器接口，用于与智能存储器子系统进行接口。 存储器接口可以是基于硬件的或基于软件的。 在一个实施例中，实现两层接口，使得内部接口可以在连续世代上演进而不影响外部可见接口。

公开(公告)号：US08760958B2

公开(公告)日：2014-06-24

申请号：US13421704

申请日：2012-03-15

申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

IPC分类号： G11C8/00 ,  G11C8/16

CPC分类号： G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

摘要： To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

摘要翻译： 为了处理多个并发存储器请求，提出了一个双端口六晶体管（6T）SRAM位单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问位单元的真实侧和假侧。 单端读取允许内存系统同时处理两个独立的读操作。 通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 位单元格。 因此，具有电压辅助的单端操作允许存储器系统处理两个并行写入操作。 可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

公开(公告)号：US08433880B2

公开(公告)日：2013-04-30

申请号：US12584645

申请日：2009-09-08

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F12/00

CPC分类号： G06F12/0292 ,  G06F12/06 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/502 ,  G06F2212/657

摘要： A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict.

摘要翻译： 公开了一种用于提供高速存储器操作的系统和方法。 该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。 更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。

公开(公告)号：US07657706B2

公开(公告)日：2010-02-02

申请号：US11016572

申请日：2004-12-17

申请人： Sundar Iyer ,  Nick McKeown

发明人： Sundar Iyer ,  Nick McKeown

IPC分类号： G06F13/00

CPC分类号： G06F13/1668 ,  G06F12/0223 ,  G06F12/0607 ,  G06F2212/205

摘要： An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.

摘要翻译： 提出了一种用于加速处理器的输入/输出和存储器访问操作的输入/输出处理器。 输入/输出处理器的关键思想是将输入/输出和存储器访问操作任务功能划分为由处理器处理的计算密集型部分以及I / O或存储器密集部分，然后由输入/输出处理 处理器。 输入/输出处理器是通过分析常用的输入/输出和存储器访问模式来设计的，并且实现了有效处理这些常见模式的方法。 输入/输出处理器可以使用的一种技术是将存储器任务分为高频或高可用性组件以及低频或低可用性组件。 在以这种方式分配存储器任务之后，输入/输出处理器然后使用高速存储器（例如SRAM）来存储高频和高可用性组件以及较慢速存储器（例如商品DRAM）来存储 低频和低可用性组件。 输入/输出处理器使用的另一技术是以消除所有存储器组冲突的方式分配存储器。 通过消除任何可能的存储体冲突，可以实现DRAM存储器技术的最大随机存取性能。

公开(公告)号：US06457061B1

公开(公告)日：2002-09-24

申请号：US09199839

申请日：1998-11-24

申请人： Subhash Bal ,  Raghunath Iyer ,  Sundar Iyer

发明人： Subhash Bal ,  Raghunath Iyer ,  Sundar Iyer

IPC分类号： G06F1516

CPC分类号： H04L29/12377 ,  H04L29/12009 ,  H04L29/12481 ,  H04L61/2517 ,  H04L61/2557

摘要： A method and apparatus for performing network address translation is disclosed. The method generates statistically unique port number for each outgoing connection. The statistically unique port numbers are formed from a subset of bits from the source node's IP address and a subset of bits from the port number assigned by the source node. The statistically unique port number is used as an index into a table containing connection information. When a statistically unique port number fails to be absolutely unique, the method uses a secondary fallback system that generates a unique port number by using sequential numbering system. The information about the connections using unique port numbers that were generated sequentially is stored in a secondary connection table. The secondary connection table is organized as a Patricia tree.

摘要翻译： 公开了一种用于执行网络地址转换的方法和装置。 该方法为每个传出连接生成统计唯一的端口号。 统计唯一的端口号由来自源节点的IP地址的位的子集以及由源节点分配的端口号的位的子集形成。 统计唯一的端口号用作包含连接信息的表的索引。 当统计唯一的端口号不能绝对唯一时，该方法使用辅助回退系统，通过使用顺序编号系统生成唯一的端口号。 关于使用连续生成的唯一端口号的连接的信息存储在辅助连接表中。 辅助连接表被组织为Patricia树。

公开(公告)号：US09442846B2

公开(公告)日：2016-09-13

申请号：US12806631

申请日：2010-08-17

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F3/0629 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0673 ,  G06F12/08 ,  G06F2212/254

摘要： A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created.

摘要翻译： 公开了一种用于设计和构造分层存储器系统的系统和方法。 公开了多种不同的算法存储器块。 每个算法存储器块包括实现特定存储算法和一组较低级存储器组件的存储器控​​制器。 这些较低级存储器组件中的每一个可以用另一个算法存储器块或基本存储器块来构造。 通过在各种不同的分层组织中组织算法存储器块，可以创建提供新特征的不同复杂的存储器系统。

公开(公告)号：US09293187B2

公开(公告)日：2016-03-22

申请号：US13245426

申请日：2011-09-26

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F12/06 ,  G11C11/406

CPC分类号： G11C11/40603 ,  G11C11/40618

摘要： Dynamic memory systems require each memory cell to be continually refreshed. During a memory refresh operation, the refreshed memory cells cannot be accessed by a memory read or write operation. In multi-bank dynamic memory systems, concurrent refresh systems allow memory refresh circuitry to refresh memory banks that are not currently involved in memory access operations. To efficiently refresh memory banks and advanced round robin refresh system refreshes memory banks in a nominal round robin manner but skips memory banks blocked by memory access operations. Skipped memory banks are prioritized and then refreshed when they are no longer blocked.

摘要翻译： 动态存储器系统要求每个存储单元被不断刷新。 在存储器刷新操作期间，刷新的存储器单元不能被存储器读或写操作访问。 在多行动态存储器系统中，并发刷新系统允许存储器刷新电路来刷新当前不参与存储器存取操作的存储器组。 为了有效地刷新内存库和高级循环刷新系统，以一种名义上的循环方式刷新内存库，但是忽略了内存访问操作阻塞的内存块。 跳过的内存库被优先排列，然后在不再被阻止时刷新。

公开(公告)号：US09058860B2

公开(公告)日：2015-06-16

申请号：US13434296

申请日：2012-03-29

申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C8/16 ,  G11C11/413

CPC分类号： G06F17/505 ,  G06F17/5072 ,  G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

摘要： Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

摘要翻译： 现代数字集成电路中通常需要多端口存储器电路来存储数据。 多端口存储器电路允许多个存储器用户同时访问相同的存储器单元。 多端口存储器电路通常是为了获得最佳性能而定制设计的，或者通过用于快速设计的逻辑综合工具来合成。 然而，创建多端口存储器的这两个选项为集成电路设计师提供了一个明显的选择：投入大量的时间和金钱来定制设计高效的多端口存储器系统，或允许逻辑综合工具低效地创建多端口存储器。 公开了一种中间解决方案，其允许使用标准电路单元组件和寄存器传输级硬件设计语言代码来大量创建有效的多端口存储器阵列。

公开(公告)号：US08902672B2

公开(公告)日：2014-12-02

申请号：US13732372

申请日：2013-01-01

申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian ,  Kartik Mohanram

发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian ,  Kartik Mohanram

IPC分类号： G11C8/16 ,  G11C11/419 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C11/419 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  G11C11/412

摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.

摘要翻译： 大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据。 为了处理多个内存用户，提出了一种高效的双端口六晶体管（6T）SRAM存储单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立访问SRAM单元的真实面和假面。 单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个读取。 可以更快地处理写入操作，使得可以使用时分复用在单个周期中处理两个写入操作。 为了进一步提高双端口6T SRAM单元的运行，采用了多种算法技术来改善存储系统的运行。

公开(公告)号：USRE45097E1

公开(公告)日：2014-08-26

申请号：US13365136

申请日：2012-02-02

申请人： Sundar Iyer ,  Nick McKeown

发明人： Sundar Iyer ,  Nick McKeown

IPC分类号： G06F13/00

CPC分类号： G06F13/1668 ,  G06F12/0223 ,  G06F12/0607 ,  G06F2212/205

摘要： An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.

摘要翻译： 提出了一种用于加速处理器的输入/输出和存储器访问操作的输入/输出处理器。 输入/输出处理器的关键思想是将输入/输出和存储器访问操作任务功能划分为由处理器处理的计算密集型部分以及I / O或存储器密集部分，然后由输入/输出处理 处理器。 输入/输出处理器是通过分析常用的输入/输出和存储器访问模式来设计的，并且实现了有效处理这些常见模式的方法。 输入/输出处理器可以使用的一种技术是将存储器任务分为高频或高可用性组件以及低频或低可用性组件。 在以这种方式分配存储器任务之后，输入/输出处理器然后使用高速存储器（例如SRAM）来存储高频和高可用性组件以及较慢速存储器（例如商品DRAM）来存储 低频和低可用性组件。 输入/输出处理器使用的另一技术是以消除所有存储器组冲突的方式分配存储器。 通过消除任何可能的存储体冲突，可以实现DRAM存储器技术的最大随机存取性能。