公开(公告)号：US20190007070A1

公开(公告)日：2019-01-03

申请号：US15640724

申请日：2017-07-03

Applicant: Seagate Technology LLC

Inventor： Jeffrey John Pream ,  Eric Michael Beck

IPC: H03M13/37 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11

Abstract: Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a non-volatile memory (NVM) is configured to store data in the form of code words. Each code word has a user data payload and associated code bits. A plurality of data decoder circuits are configured to use the code bits to detect and correct bit errors in the code words during a read operation. A power transition circuit is configured to successively transition each of the data decoder circuits in turn from a first power mode to a second power mode, such as from an active mode to an idle mode, at a different time and at a conclusion of a predetermined time interval. In this way, voltage spikes or other anomalous conditions on a voltage source pathway may be reduced.

公开(公告)号：US10171110B1

公开(公告)日：2019-01-01

申请号：US15640724

申请日：2017-07-03

Applicant: Seagate Technology LLC

Inventor： Jeffrey John Pream ,  Eric Michael Beck

IPC: H03M13/37 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G11C11/4072 ,  G11C29/00

Abstract: Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a non-volatile memory (NVM) is configured to store data in the form of code words. Each code word has a user data payload and associated code bits. A plurality of data decoder circuits are configured to use the code bits to detect and correct bit errors in the code words during a read operation. A power transition circuit is configured to successively transition each of the data decoder circuits in turn from a first power mode to a second power mode, such as from an active mode to an idle mode, at a different time and at a conclusion of a predetermined time interval. In this way, voltage spikes or other anomalous conditions on a voltage source pathway may be reduced.