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公开(公告)号：US20190007070A1
公开(公告)日：2019-01-03
申请号：US15640724
申请日：2017-07-03
Applicant: Seagate Technology LLC
Inventor： Jeffrey John Pream , Eric Michael Beck
Abstract: Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a non-volatile memory (NVM) is configured to store data in the form of code words. Each code word has a user data payload and associated code bits. A plurality of data decoder circuits are configured to use the code bits to detect and correct bit errors in the code words during a read operation. A power transition circuit is configured to successively transition each of the data decoder circuits in turn from a first power mode to a second power mode, such as from an active mode to an idle mode, at a different time and at a conclusion of a predetermined time interval. In this way, voltage spikes or other anomalous conditions on a voltage source pathway may be reduced.
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公开(公告)号：US10802756B1
公开(公告)日：2020-10-13
申请号：US16033607
申请日：2018-07-12
Applicant: Seagate Technology LLC
Inventor： Jeffrey John Pream , Jeremy Blair Goolsby
Abstract: Systems and methods are disclosed for command status polling at a flash queue of a non-volatile memory device. The flash queue may be configured to perform polling on the status of flash operations without direct oversight from the data storage controller or firmware. In certain embodiments, a flash queue circuit may be configured to receive, from a data storage controller of a nonvolatile solid state memory (NVSSM) data storage device, one or more commands to access a flash memory of the NVSSM data storage device, each command of the one or more commands including one or more instructions. The flash queue circuit may execute the one or more commands to access the flash memory, evaluate a status response from the flash memory at the flash queue circuit, and re-execute a sequence of instructions of the one or more commands based on the status response.
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公开(公告)号：US09280422B2
公开(公告)日：2016-03-08
申请号：US14020630
申请日：2013-09-06
Applicant: Seagate Technology LLC
Inventor： Jeffrey John Pream , Ara Patapoutian
CPC classification number: G06F11/108 , G06F11/1048
Abstract: A device comprising a data transfer channel is configured to transfer data between multiple memory devices and a host device. The channel includes multiple decoders and a buffer coupled between the multiple memory devices and the multiple decoders. The buffer is configured to store code words received from the memory devices. Channel control logic is configured to determine availability of one or more of the multiple decoders and to distribute the code words to the one or more decoders based on decoder availability.
Abstract translation: 包括数据传输通道的设备被配置为在多个存储器设备和主机设备之间传送数据。 信道包括多个解码器和耦合在多个存储器件和多个解码器之间的缓冲器。 缓冲器被配置为存储从存储器件接收的代码字。 信道控制逻辑被配置为确定多个解码器中的一个或多个解码器的可用性，并且基于解码器可用性将码字分发到一个或多个解码器。
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公开(公告)号：US10171110B1
公开(公告)日：2019-01-01
申请号：US15640724
申请日：2017-07-03
Applicant: Seagate Technology LLC
Inventor： Jeffrey John Pream , Eric Michael Beck
Abstract: Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a non-volatile memory (NVM) is configured to store data in the form of code words. Each code word has a user data payload and associated code bits. A plurality of data decoder circuits are configured to use the code bits to detect and correct bit errors in the code words during a read operation. A power transition circuit is configured to successively transition each of the data decoder circuits in turn from a first power mode to a second power mode, such as from an active mode to an idle mode, at a different time and at a conclusion of a predetermined time interval. In this way, voltage spikes or other anomalous conditions on a voltage source pathway may be reduced.
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Patent Agency Ranking
公开(公告)号：US20150074677A1
公开(公告)日：2015-03-12
申请号：US14020624
申请日：2013-09-06
Applicant: Seagate Technology LLC
Inventor： Jeffrey John Pream , Purushothaman Bijoy , Venugopal Rao Garuda , Ara Patapoutian
IPC: G06F9/50
CPC classification number: G06F9/5083 , G06F9/5016 , G06F2209/5021 , G06F2209/507 , Y02D10/22
Abstract: A load adaptive pipeline system includes a data recovery pipeline configured to transfer data between a memory and a host. The pipeline includes a plurality of resources, one or more of the plurality of resources in the pipeline have multiple resource components available for allocation. The system includes a pipeline controller configured to assess at least one parameter affecting data transfer through the pipeline. The pipeline controller is configure to allocate resource components to the one or more resources in the pipeline in response to assessment of the at least one data transfer parameter.
Abstract translation: 负载自适应流水线系统包括被配置为在存储器和主机之间传送数据的数据恢复流水线。 管线包括多个资源，管道中的多个资源中的一个或多个资源具有可用于分配的多个资源组件。 该系统包括流水线控制器，其被配置为评估影响通过流水线的数据传输的至少一个参数。 流水线控制器被配置为响应于至少一个数据传输参数的评估将资源组件分配给流水线中的一个或多个资源。
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公开(公告)号：US11429315B1
公开(公告)日：2022-08-30
申请号：US17016502
申请日：2020-09-10
Applicant: Seagate Technology LLC
Inventor： Jeffrey John Pream , Jeremy Blair Goolsby
Abstract: Systems and methods are disclosed for command status polling at a flash queue of a non-volatile memory device. The flash queue may be configured to perform polling on the status of flash operations without direct oversight from the data storage controller or firmware. In certain embodiments, a flash queue circuit may be configured to receive, from a data storage controller of a nonvolatile solid state memory (NVSSM) data storage device, one or more commands to access a flash memory of the NVSSM data storage device, each command of the one or more commands including one or more instructions. The flash queue circuit may execute the one or more commands to access the flash memory, evaluate a status response from the flash memory at the flash queue circuit, and re-execute a sequence of instructions of the one or more commands based on the status response.
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公开(公告)号：US11233528B1
公开(公告)日：2022-01-25
申请号：US17022549
申请日：2020-09-16
Applicant: Seagate Technology LLC
Inventor： Ivana Djurdjevic , Ara Patapoutian , Deepak Sridhara , Bengt Anders Ulriksson , Jeffrey John Pream
IPC: H03M13/11
Abstract: A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.
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公开(公告)号：US09323584B2
公开(公告)日：2016-04-26
申请号：US14020624
申请日：2013-09-06
Applicant: Seagate Technology LLC
Inventor： Jeffrey John Pream , Bijoy Purushothaman , Venugopal Rao Garuda , Ara Patapoutian
CPC classification number: G06F9/5083 , G06F9/5016 , G06F2209/5021 , G06F2209/507 , Y02D10/22
Abstract: A load adaptive pipeline system includes a data recovery pipeline configured to transfer data between a memory and a host. The pipeline includes a plurality of resources, one or more of the plurality of resources in the pipeline have multiple resource components available for allocation. The system includes a pipeline controller configured to assess at least one parameter affecting data transfer through the pipeline. The pipeline controller is configure to allocate resource components to the one or more resources in the pipeline in response to assessment of the at least one data transfer parameter.
Abstract translation: 负载自适应流水线系统包括被配置为在存储器和主机之间传送数据的数据恢复流水线。 管线包括多个资源，管道中的多个资源中的一个或多个资源具有可用于分配的多个资源组件。 该系统包括流水线控制器，其被配置为评估影响通过流水线的数据传输的至少一个参数。 流水线控制器被配置为响应于至少一个数据传输参数的评估将资源组件分配给流水线中的一个或多个资源。
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公开(公告)号：US20150074488A1
公开(公告)日：2015-03-12
申请号：US14020630
申请日：2013-09-06
Applicant: Seagate Technology LLC
Inventor： Jeffrey John Pream , Ara Patapoutian
IPC: G06F11/10
CPC classification number: G06F11/108 , G06F11/1048
Abstract: A device comprising a data transfer channel is configured to transfer data between multiple memory devices and a host device. The channel includes multiple decoders and a buffer coupled between the multiple memory devices and the multiple decoders. The buffer is configured to store code words received from the memory devices. Channel control logic is configured to determine availability of one or more of the multiple decoders and to distribute the code words to the one or more decoders based on decoder availability.
Abstract translation: 包括数据传输通道的设备被配置为在多个存储器设备和主机设备之间传送数据。 信道包括多个解码器和耦合在多个存储器件和多个解码器之间的缓冲器。 缓冲器被配置为存储从存储器件接收的代码字。 信道控制逻辑被配置为确定多个解码器中的一个或多个解码器的可用性，并且基于解码器可用性将码字分发到一个或多个解码器。
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