公开(公告)号：US09478249B2

公开(公告)日：2016-10-25

申请号：US14014912

申请日：2013-08-30

Applicant: Seagate Technology LLC

Inventor： Jun Cheol Kim ,  Hye Jeong Nam ,  Jae Ik Song

IPC: G11B20/12 ,  G11B20/10

CPC classification number: G11B20/1252 ,  G11B2020/10916 ,  G11B2020/1295

Abstract: Implementations disclosed herein provide for sequential readback of program data in from a cached data region of a storage device. In particular, the disclosed technology provides for storing a sequence of logical addresses associated with execution of a program, the sequence of logical addresses including at least two consecutive logical addresses associated with non-consecutive data blocks in a user data region; writing data corresponding to the at least two consecutive logical addresses to sequential data blocks in a cached data region; determining that a sequence of read commands from a host computer is associated with the data; and reading the data from the cached data region.

Abstract translation: 本文公开的实施方案提供了从存储设备的缓存数据区域中的程序数据的顺序回读。 特别地，所公开的技术提供存储与程序的执行相关联的逻辑地址序列，所述逻辑地址序列包括与用户数据区域中的非连续数据块相关联的至少两个连续的逻辑地址; 将对应于所述至少两个连续的逻辑地址的数据写入缓存的数据区域中的顺序数据块; 确定来自主计算机的读取命令的序列与所述数据相关联; 并从缓存的数据区读取数据。

公开(公告)号：US20160077974A1

公开(公告)日：2016-03-17

申请号：US14484616

申请日：2014-09-12

Applicant: Seagate Technology LLC

Inventor： Jun Cheol Kim ,  Hye Jeong Nam ,  Sang Yeel Ji

IPC: G06F12/08

CPC classification number: G06F12/0868 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/312 ,  G06F2212/502

Abstract: Technologies are described herein for adaptively controlling the size of a write cache in a storage device based on the time required to flush the cache. Upon receiving a write command at a controller for the storage device, an estimated cache flush time for the write cache is calculated based on the write commands contained therein. If the estimated cache flush time is greater than a maximum threshold time, the size of the write cache is decreased to control the cache flush time. If the estimated cache flush time is less than a minimum threshold time, the size of the write cache is increased to enhance random write performance.

Abstract translation: 本文描述了技术，以基于刷新高速缓存所需的时间自适应地控制存储设备中的写入高速缓存的大小。 在存储装置的控制器处接收到写入命令时，基于其中包含的写入命令来计算用于写入高速缓存的估计的高速缓存刷新时间。 如果估计的高速缓存刷新时间大于最大阈值时间，则减少写入高速缓存的大小以控制高速缓存刷新时间。 如果估计的缓存刷新时间小于最小阈值时间，则增加写入高速缓存的大小以增强随机写入性能。

公开(公告)号：US20150062736A1

公开(公告)日：2015-03-05

申请号：US14014912

申请日：2013-08-30

Applicant: Seagate Technology LLC

Inventor： Jun Cheol Kim ,  Hye Jeong Nam ,  Jae Ik Song

IPC: G11B20/12

CPC classification number: G11B20/1252 ,  G11B2020/10916 ,  G11B2020/1295

Abstract: Implementations disclosed herein provide for sequential readback of program data in from a cached data region of a storage device. In particular, the disclosed technology provides for storing a sequence of logical addresses associated with execution of a program, the sequence of logical addresses including at least two consecutive logical addresses associated with non-consecutive data blocks in a user data region; writing data corresponding to the at least two consecutive logical addresses to sequential data blocks in a cached data region; determining that a sequence of read commands from a host computer is associated with the data; and reading the data from the cached data region.

Abstract translation: 本文公开的实施方案提供了从存储设备的缓存数据区域中的程序数据的顺序回读。 特别地，所公开的技术提供存储与程序的执行相关联的逻辑地址序列，所述逻辑地址序列包括与用户数据区域中的非连续数据块相关联的至少两个连续的逻辑地址; 将对应于所述至少两个连续的逻辑地址的数据写入缓存的数据区域中的顺序数据块; 确定来自主计算机的读取命令的序列与所述数据相关联; 并从缓存的数据区读取数据。