Fast cache with intelligent copyback

    公开(公告)号:US11640336B2

    公开(公告)日:2023-05-02

    申请号:US17380655

    申请日:2021-07-20

    IPC分类号: G06F11/10 G06F11/07 G06F3/06

    摘要: Method and apparatus for intelligent caching, protection and transfers of data between a cache and a main memory in a data storage environment, such as but not limited to a solid-state drive (SSD). A main memory (MM) has non-volatile memory (NVM) cells configured for persistent storage of user data. A fast response cache (FRC) has NVM cells configured to provide storage of first data prior to transfer to the MM. A write cache (WC) has NVM cells configured to provide storage of second data prior to transfer to the MM. A controller directs input data to either the FRC or the WC. A first type of error correction encoding (ECC1) is applied to the first data and a different, second type of error correction encoding (ECC2) is applied to the second data. Data may be sent from the FRC to the MM either directly or through the WC.

    FAST CACHE WITH INTELLIGENT COPYBACK

    公开(公告)号:US20220027234A1

    公开(公告)日:2022-01-27

    申请号:US17380655

    申请日:2021-07-20

    IPC分类号: G06F11/10 G06F11/07 G06F3/06

    摘要: Method and apparatus for intelligent caching, protection and transfers of data between a cache and a main memory in a data storage environment, such as but not limited to a solid-state drive (SSD). A main memory (MM) has non-volatile memory (NVM) cells configured for persistent storage of user data. A fast response cache (FRC) has NVM cells configured to provide storage of first data prior to transfer to the MM. A write cache (WC) has NVM cells configured to provide storage of second data prior to transfer to the MM. A controller directs input data to either the FRC or the WC. A first type of error correction encoding (ECC1) is applied to the first data and a different, second type of error correction encoding (ECC2) is applied to the second data. Data may be sent from the FRC to the MM either directly or through the WC.

    Pre-suspend before program in a non-volatile memory (NVM)

    公开(公告)号:US12086462B2

    公开(公告)日:2024-09-10

    申请号:US17381342

    申请日:2021-07-21

    IPC分类号: G06F3/06 G06F12/02

    摘要: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). An apparatus includes a main non-volatile memory (NVM) such as a NAND flash memory. A host command queue lists pending data transfer commands to transfer data between the NVM and a host. For each write command received by the NVM to store write data to an associated target location, a controller examines the host command queue. Based on this review, the controller may direct the NVM to read data adjacent the associated target location to which data are to be written by the write command and to transfer the read data to a read cache. The read data may use some or all of the same resources used to store the write data to the NVM. The read data may be subsequently transferred from the read cache to the host.

    Collision reduction through just-in-time resource allocation

    公开(公告)号:US11698734B2

    公开(公告)日:2023-07-11

    申请号:US17380708

    申请日:2021-07-20

    IPC分类号: G06F3/06

    摘要: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a main memory has memory cells arranged on dies arranged as die sets accessible using parallel channels. A controller is configured to arbitrate resources required by access commands to transfer data to or from the main memory using the parallel channels, to monitor an occurrence rate of collisions between commands requiring an overlapping set of the resources, and to adjust a ratio among different types of commands executed by the controller responsive to the occurrence rate of the collisions. In further embodiments, the controller may divide a full command into multiple partial commands, each of which are executed as the associated system resources become available. In some cases, the ratio is established between read commands and write commands issued to the main memory.

    PRE-SUSPEND BEFORE PROGRAM IN A NON-VOLATILE MEMORY (NVM)

    公开(公告)号:US20220035566A1

    公开(公告)日:2022-02-03

    申请号:US17381342

    申请日:2021-07-21

    IPC分类号: G06F3/06 G06F12/02

    摘要: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). An apparatus includes a main non-volatile memory (NVM) such as a NAND flash memory. A host command queue lists pending data transfer commands to transfer data between the NVM and a host. For each write command received by the NVM to store write data to an associated target location, a controller examines the host command queue. Based on this review, the controller may direct the NVM to read data adjacent the associated target location to which data are to be written by the write command and to transfer the read data to a read cache. The read data may use some or all of the same resources used to store the write data to the NVM. The read data may be subsequently transferred from the read cache to the host.

    COLLISION REDUCTION THROUGH JUST-IN-TIME RESOURCE ALLOCATION

    公开(公告)号:US20220027069A1

    公开(公告)日:2022-01-27

    申请号:US17380708

    申请日:2021-07-20

    IPC分类号: G06F3/06

    摘要: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a main memory has memory cells arranged on dies arranged as die sets accessible using parallel channels. A controller is configured to arbitrate resources required by access commands to transfer data to or from the main memory using the parallel channels, to monitor an occurrence rate of collisions between commands requiring an overlapping set of the resources, and to adjust a ratio among different types of commands executed by the controller responsive to the occurrence rate of the collisions. In further embodiments, the controller may divide a full command into multiple partial commands, each of which are executed as the associated system resources become available. In some cases, the ratio is established between read commands and write commands issued to the main memory.