公开(公告)号：US10929025B2

公开(公告)日：2021-02-23

申请号：US16451841

申请日：2019-06-25

Applicant: Seagate Technology LLC

Inventor： Michael Shaw

IPC: G06F3/06

Abstract: In a data storage system, latency optimization can be practiced by logging a plurality of data accesses to a memory in a register with each data access of the plurality of data accesses corresponding with a command generated by a host connected to the memory. The register may be analyzed with a system module to predict a command execution latency value for the plurality of data accesses that can be used to generate a deterministic data access sequence with the system module. A queue of data accesses can then be reorganized from a first sequence to the deterministic data access sequence to reduce command execution latency variability during a deterministic window selected by the host.

公开(公告)号：US11481342B2

公开(公告)日：2022-10-25

申请号：US16451864

申请日：2019-06-25

Applicant: Seagate Technology LLC

Inventor： Robert Wayne Moss ,  Michael Shaw ,  Thomas V. Spencer ,  Yalan Liu ,  Sarvani Reddy Kolli

IPC: G06F13/16 ,  G06F9/50 ,  G06F11/07 ,  G06F12/02 ,  G06F11/10

Abstract: A data storage system can organize a semiconductor memory into a first data set and a second data set with a first queue populated with a first data access request from a host. An assignment of an arbitration weight to the first queue with an arbitration circuit corresponds with the first queue being skipped during a deterministic window based on the arbitration weight.