公开(公告)号：US20210272983A1

公开(公告)日：2021-09-02

申请号：US17084940

申请日：2020-10-30

Applicant: Seagate Technology LLC

Inventor： Ian J. Gilbert ,  Steven D. Granz ,  Jon D. Trantham

IPC: H01L27/11597 ,  H01L27/24 ,  H01L45/00 ,  H01L27/1159 ,  H01L29/51 ,  H01L29/78

Abstract: A memory device has ferroelectric memory cells arranged into a three-dimensional (3D) structure. Each ferroelectric memory cell has a ferroelectric layer adapted to provide non-volatile storage of data. In some cases, each ferroelectric memory cell is arranged as a ferroelectric field effect transistor (FeFET) comprising a source region, a drain region, and a control gate region, the control gate region comprising the ferroelectric layer. In other cases, each ferroelectric memory cell is arranged as a ferroelectric tunnel junction (FTJ) comprising opposing conductive electrode layers between which the ferroelectric layer and a tunnel junction layer are contactingly disposed. The ferroelectric layer may be formed of HfO2, ZrO2, Hf1-xZxO2, etc. The tunnel barrier layer may be formed of Al2O3, MgO, SrTiO3, etc. The memory can be used as a substitute for DRAM, a main memory in a data storage device, a data cache, etc.