公开(公告)号：US12176810B2

公开(公告)日：2024-12-24

申请号：US17621338

申请日：2020-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Kousuke Sasaki ,  Yuto Yakubo ,  Kei Takahashi

IPC: H02M3/156 ,  H01L27/12 ,  H01L29/786 ,  H02H7/18

Abstract: A novel oscillator, an amplifier circuit, an inverter circuit, an amplifier circuit, a battery control circuit, a battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. The semiconductor device includes an oscillator including a first transistor containing a metal oxide, and a second transistor to a fifth transistor, in which a first potential is supplied to a gate of the second transistor and a gate of the third transistor when the first transistor is turned on, and the first potential is held when the first transistor is turned off. The oscillator supplies a first signal based on the first potential to a first circuit. The first circuit performs at least one of shaping and amplification on the first signal. The second transistor and the fourth transistor are connected in series, and the third transistor and the fifth transistor are connected in series. A source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, and a source or a drain of the fourth transistor is electrically connected to the gate of the third transistor.

公开(公告)号：US11908947B2

公开(公告)日：2024-02-20

申请号：US17628091

申请日：2020-07-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro Kozuma ,  Takahiko Ishizu ,  Takeshi Aoki ,  Masashi Fujita ,  Kazuma Furutani ,  Kousuke Sasaki

IPC: G11C7/10 ,  H01L29/786 ,  G06F7/544 ,  G11C7/12 ,  G11C7/14 ,  H10B12/00 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G06F7/5443 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/14 ,  H10B12/50 ,  H01L27/1225

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.