公开(公告)号：US20160211267A1

公开(公告)日：2016-07-21

申请号：US15083364

申请日：2016-03-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Takashi OKUDA

IPC: H01L27/112 ,  H01L27/06 ,  H01L29/78 ,  H01L27/12 ,  H01L29/16 ,  H01L29/786 ,  H01L27/108

CPC classification number: H01L21/76801 ,  H01L21/76826 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/112 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/16 ,  H01L29/78 ,  H01L29/7869

Abstract: Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.