公开(公告)号：US08427195B1

公开(公告)日：2013-04-23

申请号：US13468668

申请日：2012-05-10

申请人： Seong Kwan Lee ,  Hyun Woo Choi ,  Sung Yeol Kim ,  David Keezer ,  Carl Gray ,  Te-Hui Chen

发明人： Seong Kwan Lee ,  Hyun Woo Choi ,  Sung Yeol Kim ,  David Keezer ,  Carl Gray ,  Te-Hui Chen

IPC分类号： H03K19/00

CPC分类号： H03K19/21 ,  H03K2005/00241

摘要： A digital signal generator includes an input unit configured to receive signal information of a target data signal, a controller configured to calculate at least two delay values and at least two data values, the at least two delay values and the at least two data values being used to generate a data signal corresponding to the signal information input through the input unit, a multi-phase clock generator configured to delay a reference clock signal based on the at least two delay values to generate at least two clock signals having different phases, a signal generator configured to generate at least two data signals by assigning the at least two data values to the at least two clock signals, and a logic gate unit configured to generate the data signal corresponding to the signal information input through the input unit based on the at least two data signals.

摘要翻译： 数字信号发生器包括被配置为接收目标数据信号的信号信息的输入单元，配置成计算至少两个延迟值和至少两个数据值的控制器，所述至少两个延迟值和至少两个数据值是 用于产生与通过输入单元输入的信号信息相对应的数据信号;多相时钟发生器，被配置为基于所述至少两个延迟值来延迟参考时钟信号，以产生具有不同相位的至少两个时钟信号; 信号发生器，被配置为通过将至少两个数据值分配给所述至少两个时钟信号来产生至少两个数据信号;以及逻辑门单元，被配置为基于所述至少两个时钟信号生成与通过所述输入单元输入的信号信息相对应的数据信号 至少两个数据信号。