公开(公告)号：US07480166B2

公开(公告)日：2009-01-20

申请号：US11442902

申请日：2006-05-30

申请人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C17/00

CPC分类号： G11C17/126

摘要： A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

公开(公告)号：US07075809B2

公开(公告)日：2006-07-11

申请号：US10869386

申请日：2004-06-16

申请人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C17/00

CPC分类号： G11C17/126

摘要： A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

公开(公告)号：US20060215436A1

公开(公告)日：2006-09-28

申请号：US11442902

申请日：2006-05-30

申请人： Seong-ho Jeung ,  Young-Keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Seong-ho Jeung ,  Young-Keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C17/00

CPC分类号： G11C17/126

摘要： A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

公开(公告)号：US20050018465A1

公开(公告)日：2005-01-27

申请号：US10869386

申请日：2004-06-16

申请人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C17/14 ,  G11C17/12 ,  G11C17/00

CPC分类号： G11C17/126

摘要： A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

摘要翻译： 金属（或通过）可编程ROM的存储单元结构，由此在可编程ROM的位单元之间共享晶体管。 这样的存储单元结构可以包括：字线; 有点线 第一和第二虚拟接地线; 接地线 由字线和第一虚拟接地线的信号选择的第一位单元; 以及由字线和第二虚拟接地线的信号选择的第二位单元，其中单元晶体管的一侧连接到位线由第一和第二位单元共享。 此外，单元晶体管的另一侧可以浮置或连接到位线，或者替代地，连接到第一虚拟接地线，第二虚拟接地线和接地线中的任一个，以及单元晶体管的栅极 连接到字线。

公开(公告)号：US06771528B2

公开(公告)日：2004-08-03

申请号：US10085367

申请日：2002-02-28

申请人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

发明人： Seong-ho Jeung ,  Young-keun Lee ,  Yong-jae Choo ,  Young-sook Do

IPC分类号： G11C700

CPC分类号： G11C17/126

摘要： A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

摘要翻译： 金属（或通过）可编程ROM的存储单元结构，由此在可编程ROM的位单元之间共享晶体管。 这样的存储单元结构可以包括：字线; 有点线 第一和第二虚拟接地线; 接地线 由字线和第一虚拟接地线的信号选择的第一位单元; 以及由字线和第二虚拟接地线的信号选择的第二位单元，其中单元晶体管的一侧连接到位线由第一和第二位单元共享。 此外，单元晶体管的另一侧可以浮置或连接到位线，或者替代地，连接到第一虚拟接地线，第二虚拟接地线和接地线中的任一个，以及单元晶体管的栅极 连接到字线。

公开(公告)号：US07075838B2

公开(公告)日：2006-07-11

申请号：US10756715

申请日：2004-01-13

申请人： Seong-ho Jeung ,  Jong-hoon Jung

发明人： Seong-ho Jeung ,  Jong-hoon Jung

IPC分类号： G11C29/06 ,  G11C29/50 ,  G11C11/413 ,  G11C8/08

CPC分类号： G11C29/12 ,  G11C11/41 ,  G11C2029/1202 ,  G11C2029/1802

摘要： A semiconductor device and a method of testing the semiconductor device are provided. The semiconductor device includes a memory cell array, a sense amplifier, a control circuit, a row decoder, a bitline-pair voltage setting circuit, and a wordline driver. The memory cell array is connected to one of a plurality of wordlines and a plurality of bitline pairs. The memory cell array comprises a plurality of memory cells, wherein each memory cell is connected to one of the plurality of wordlines and the plurality of bitline pairs. The sense amplifier amplifies data read from the memory cell array. The control circuit controls writing/reading of data to/from the memory cell array. The row decoder decodes an address signal and outputs a decoded signal to select one of the plurality of wordlines. The bitline-pair voltage setting circuit sets the voltage of at least one of the plurality of bitline pairs to a bitline test voltage in a test mode. The wordline driver sets the low-level voltages of the plurality of wordlines to a wordline test voltage in the test mode. The wordline test voltage level can be set to be different from the low-level voltage of the plurality of wordlines in a normal operation mode.

摘要翻译： 提供半导体器件和测试半导体器件的方法。 半导体器件包括存储单元阵列，读出放大器，控制电路，行解码器，位线对电压设置电路和字线驱动器。 存储单元阵列连接到多个字线和多个位线对之一。 存储单元阵列包括多个存储器单元，其中每个存储器单元连接到多个字线和多个位线对之一。 读出放大器放大从存储单元阵列读出的数据。 控制电路控制向/从存储单元阵列写入/读取数据。 行解码器解码地址信号并输出​​解码信号以选择多个字线中的一个。 位线对电压设定电路在测试模式中将多个位线对中的至少一个的电压设置为位线测试电压。 字线驱动器将测试模式中的多个字线的低电平电压设置为字线测试电压。 字线测试电压电平可以被设置为与正常操作模式中的多个字线的低电平电压不同。

公开(公告)号：US06798700B2

公开(公告)日：2004-09-28

申请号：US10718344

申请日：2003-11-20

申请人： Seong-ho Jeung

发明人： Seong-ho Jeung

IPC分类号： G11C1604

CPC分类号： G11C8/16 ,  G11C11/419

摘要： Methods can be provided for reading data from a memory device comprising a plurality of memory cells and a plurality of virtual ground lines wherein each memory cell comprises a latch circuit coupled to a read circuit and wherein each virtual ground line is coupled with read circuits of a respective group of memory cells. Methods for reading according to embodiments of the present invention can include selecting a memory cell from which data is to be read, applying a first reference voltage to a virtual ground line coupled to the selected memory cell from which data is to be read, and applying a second reference voltage to a virtual ground line not coupled to the selected memory cell. A read word line coupled to the read circuit of the selected memory cell from which data is to be read can be activated. Responsive to activating the read word line coupled to the read circuit of the selected memory cell from which data is to be read, data can be coupled from the latch circuit of the selected memory cell with a respective read bit line through the read circuit of the selected memory cell. Methods of writing are also discussed, as are related memory devices and cells.

摘要翻译： 可以提供用于从包括多个存储器单元和多个虚拟接地线的存储器件读取数据的方法，其中每个存储器单元包括耦合到读取电路的锁存电路，并且其中每个虚拟接地线与读取电路 各组存储单元。 根据本发明的实施例的用于读取的方法可以包括选择要从其读取数据的存储单元，将第一参考电压施加到耦合到要从其读取数据的所选择的存储器单元的虚拟接地线，以及应用 向未被选择的存储单元耦合的虚拟接地线的第二参考电压。 可以激活耦合到要从其读取数据的所选存储单元的读取电路的读字线。 响应于激活耦合到要从其读取数据的所选择的存储器单元的读取电路的读取字线，可以从所选择的存储器单元的锁存电路与相应的读位线耦合数据，通过读取电路的读取电路 选择的存储单元。 还讨论了写入的方法，以及相关的存储器件和单元。

公开(公告)号：US06674670B2

公开(公告)日：2004-01-06

申请号：US10123601

申请日：2002-04-16

申请人： Seong-ho Jeung

发明人： Seong-ho Jeung

IPC分类号： G11C1604

CPC分类号： G11C8/16 ,  G11C11/419

摘要： Methods can be provided for reading data from a memory device comprising a plurality of memory cells and a plurality of virtual ground lines wherein each memory cell comprises a latch circuit coupled to a read circuit and wherein each virtual ground line is coupled with read circuits of a respective group of memory cells. Methods for reading according to embodiments of the present invention can include selecting a memory cell from which data is to be read, applying a first reference voltage to a virtual ground line coupled to the selected memory cell from which data is to be read, and applying a second reference voltage to a virtual ground line not coupled to the selected memory cell. A read word line coupled to the read circuit of the selected memory cell from which data is to be read can be activated. Responsive to activating the read word line coupled to the read circuit of the selected memory cell from which data is to be read, data can be coupled from the latch circuit of the selected memory cell with a respective read bit line through the read circuit of the selected memory cell. Methods of writing are also discussed, as are related memory devices and cells.

摘要翻译： 可以提供用于从包括多个存储器单元和多个虚拟接地线的存储器件读取数据的方法，其中每个存储器单元包括耦合到读取电路的锁存电路，并且其中每个虚拟接地线与读取电路 各组存储单元。 根据本发明的实施例的用于读取的方法可以包括选择要从其读取数据的存储单元，将第一参考电压施加到耦合到要从其读取数据的所选择的存储器单元的虚拟接地线，以及应用 向未被选择的存储单元耦合的虚拟接地线的第二参考电压。 可以激活耦合到要从其读取数据的所选存储单元的读取电路的读字线。 响应于激活耦合到要从其读取数据的所选择的存储器单元的读取电路的读取字线，可以从所选择的存储器单元的锁存电路与相应的读位线耦合数据，通过读取电路的读取电路 选择的存储单元。 还讨论了写入的方法，以及相关的存储器件和单元。