Abstract:
A fin Field Effect Transistor (finFET) can include a source region and a drain region of the finFET. A gate of the finFET can cross over a fin of the finFET between the source and drain regions. First and second silicide layers can be on the source and drain regions respectively. The first and second silicide layers can include respective first and second surfaces that face the gate crossing over the fin, where the first and second surfaces are different sizes.
Abstract:
A method for driving a three dimensional (3D) display and a 3D display apparatus using the same are provided. The 3D display apparatus includes a storage unit which stores a received image; and a controller which compares a previous frame of the received image with a current frame of the received image, and determines whether or not to input an image of the current frame to a liquid crystal panel based on whether the previous frame is identical to the current frame. Therefore, a method for driving a 3D display which does not cause characteristics of a liquid crystal to be deteriorated and a 3D display apparatus using the same are provided.
Abstract:
A fin Field Effect Transistor (finFET) can include a source region and a drain region of the finFET. A gate of the finFET can cross over a fin of the finFET between the source and drain regions. First and second silicide layers can be on the source and drain regions respectively. The first and second silicide layers can include respective first and second surfaces that face the gate crossing over the fin, where the first and second surfaces are different sizes.
Abstract:
A test operation method of a memory device is provided. The test operation method includes a reference current generator generating a reference current and providing a reference voltage generated based on the reference current to one of input terminals of a sense amplifier; providing a read voltage generated based on a read current of a memory cell to another one of the input terminals of the sense amplifier; and the sense amplifier comparing the reference voltage with the read voltage.
Abstract:
A stereoscopic display apparatus includes a display panel which scans an image at a frame frequency that is an odd-numbered multiple of a field frequency, an image signal input unit which inputs an image signal to the display panel, a backlight unit which emits light to the display panel, and a shutter controller which controls an opening and a closing of a left eye shutter and a right eye shutter of shutter glasses.
Abstract:
A method for driving a three dimensional (3D) display and a 3D display apparatus using the same are provided. The 3D display apparatus includes a storage unit which stores a received image; and a controller which compares a previous frame of the received image with a current frame of the received image, and determines whether or not to input an image of the current frame to a liquid crystal panel based on whether the previous frame is identical to the current frame. Therefore, a method for driving a 3D display which does not cause characteristics of a liquid crystal to be deteriorated and a 3D display apparatus using the same are provided.
Abstract:
A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.
Abstract:
A voltage generator and methods thereof are provided. The example voltage generator may include a voltage comparison block which generates an output voltage in response to a read command, the output voltage corresponding to a difference between a reference voltage and a determination voltage and a voltage generation block which outputs the determination voltage and a comparison voltage in response to the read command, an inverse read command having a phase opposite that of the read command, a switching pulse signal and the output voltage. A first example method may include outputting a determination voltage and a comparison voltage in response to a read command, an inverse read command having a phase opposite that of the read command, a switching pulse signal and an output voltage, the output voltage generated in response to the read command and corresponding to a difference between the reference voltage and the determination voltage. A second example method may include maintaining a comparison voltage at a first voltage level if a read command is disabled and transitioning the comparison voltage to a second voltage level if the read command is enabled by discharging electric current along a first path, the first path connected to a first node coupled to at least one resistor, and a second path, the second path connected to a second node coupled with a switched capacitor circuit, the switched capacitor circuit including a capacitor which is selectively connected to the second node in response to the enabled read command.
Abstract:
A semiconductor device and a method of testing the semiconductor device are provided. The semiconductor device includes a memory cell array, a sense amplifier, a control circuit, a row decoder, a bitline-pair voltage setting circuit, and a wordline driver. The memory cell array is connected to one of a plurality of wordlines and a plurality of bitline pairs. The memory cell array comprises a plurality of memory cells, wherein each memory cell is connected to one of the plurality of wordlines and the plurality of bitline pairs. The sense amplifier amplifies data read from the memory cell array. The control circuit controls writing/reading of data to/from the memory cell array. The row decoder decodes an address signal and outputs a decoded signal to select one of the plurality of wordlines. The bitline-pair voltage setting circuit sets the voltage of at least one of the plurality of bitline pairs to a bitline test voltage in a test mode. The wordline driver sets the low-level voltages of the plurality of wordlines to a wordline test voltage in the test mode. The wordline test voltage level can be set to be different from the low-level voltage of the plurality of wordlines in a normal operation mode.
Abstract:
A three-dimensional (3D) display panel, a 3D display apparatus using the same, and a driving method thereof are provided. The 3D display apparatus includes: an image display panel which displays an image; a phase shift panel which alternately shifts a polarization direction of light outputted from the image display panel; a backlight unit which provides a backlight; and a control unit which turns off the backlight unit during a crosstalk period where the phase shift panel performs the shift operation and to turn on the backlight unit for a stabilization period after the crosstalk period.