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    SEMICONDUCTOR PACKAGE AND FORMATION METHOD THEREOF
    1.
    发明申请
    SEMICONDUCTOR PACKAGE AND FORMATION METHOD THEREOF 有权

    公开(公告)号：US20210351042A1

    公开(公告)日：2021-11-11

    申请号：US16913020

    申请日：2020-06-26

    Applicant: Shanghai Tianma Micro-Electronics Co., Ltd. ,  Shanghai AVIC OPTO Electronics Co.,Ltd.

    Inventor： Xuhui PENG ,  Kerui XI ,  Tingting CUI ,  Feng QIN ,  Jie ZHANG

    IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

    Abstract: A semiconductor package and a method of forming the semiconductor package are provided. The method includes providing a first substrate, forming a wiring structure containing at least two first wiring layers, disposing a first insulating layer between adjacent two first wiring layers, and patterning the first insulating layer to form a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The method also includes providing at least one semiconductor element each including a plurality of pins. In addition, the method includes disposing the plurality of pins of the each semiconductor element on a side of the wiring structure away from the first substrate. Further, the method includes encapsulating the at least one semiconductor element, and placing a ball on a side of the wiring structure away from the at least one semiconductor element.

    PACKAGE STRUCTURE, PACKAGING METHOD, CAMERA MODULE, AND ELECTRONIC EQUIPMENT
    3.
    发明申请
    PACKAGE STRUCTURE, PACKAGING METHOD, CAMERA MODULE, AND ELECTRONIC EQUIPMENT 有权

    公开(公告)号：US20220102406A1

    公开(公告)日：2022-03-31

    申请号：US17546740

    申请日：2021-12-09

    Applicant: Shanghai AVIC OPTO Electronics Co., Ltd. ,  Shanghai Tianma Micro-Electronics Co., Ltd.

    Inventor： Kerui XI ,  Xuhui PENG ,  Feng QIN ,  Tingting CUI ,  Zhenyu JIA

    IPC: H01L27/146 ,  H01L25/16

    Abstract: The present disclosure provides chip package structure, packaging method, camera module and electronic equipment. The package structure includes chip package module, which includes light-transmitting substrate, wiring layer located on side of light-transmitting substrate and including first metal wire, conductor located on side of wiring layer facing away from light-transmitting substrate, photosensitive chip located on side of wiring layer facing away from the light-transmitting substrate, active chip located on side of wiring layer facing away from light-transmitting substrate, and plastic encapsulation layer encapsulating photosensitive chip and active chip. The conductor includes first end electrically connected to first metal wire, and second end. The photosensitive chip includes pin electrically connected to first metal wire and has photosensitive surface facing towards light-transmitting substrate. The photosensitive surface includes photosensitive region that is not overlapping first metal wire. The active chip includes pin electrically connected to first metal wire.

    CHIP PACKAGE STRUCTURE AND CHIP PACKAGE METHOD INCLUDING BARE CHIPS WITH CAPACITOR POLAR PLATE
    4.
    发明申请
    CHIP PACKAGE STRUCTURE AND CHIP PACKAGE METHOD INCLUDING BARE CHIPS WITH CAPACITOR POLAR PLATE 审中-公开

    公开(公告)号：US20200312763A1

    公开(公告)日：2020-10-01

    申请号：US16441243

    申请日：2019-06-14

    Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

    Inventor： Kerui XI ,  Feng QIN ,  Jine LIU ,  Xiaohe LI ,  Tingting CUI ,  Xuhui PENG

    IPC: H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L49/02 ,  H01L25/16 ,  H01L21/56

    Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a first metal layer, a second metal layer, and bare chips. The bare chips include first bare chips and second bare chips. First-connecting-posts are formed on a side of the first bare chips and on a side of the second bare chips. The encapsulating layer covers the bare chips and the first-connecting-posts. The first metal layer is disposed on the side of the first-connecting-posts away from the bare chips and includes first capacitor polar plates and conductive parts. The first capacitor polar plates are electrically connected to the first-connecting-posts on the first bare chips, and the conductive parts are electrically connected to the first-connecting-posts on the second bare chips. The second metal layer is disposed on a side of the first metal layer away from the encapsulating layer and includes second capacitor polar plates electrically connected to the conductive parts.

    SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220293544A1

    公开(公告)日：2022-09-15

    申请号：US17829619

    申请日：2022-06-01

    Applicant: Shanghai Tianma Micro-Electronics Co., Ltd. ,  Shanghai AVIC OPTO Electronics Co., Ltd.

    Inventor： Feng QIN ,  Kerui XI ,  Tingting CUI ,  Jie ZHANG ,  Xuhui PENG

    IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

    Abstract: Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes the followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes expose one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.

    SEMICONDUCTOR PACKAGE AND FORMATION METHOD THEREOF
    6.
    发明申请
    SEMICONDUCTOR PACKAGE AND FORMATION METHOD THEREOF 有权

    公开(公告)号：US20230137800A1

    公开(公告)日：2023-05-04

    申请号：US18090918

    申请日：2022-12-29

    Applicant: Shanghai Tianma Micro-Electronics Co., Ltd. ,  Shanghai AVIC OPTO Electronics Co.,Ltd.

    Inventor： Xuhui PENG ,  Kerui XI ,  Tingting CUI ,  Feng QIN ,  Jie ZHANG

    IPC: H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

    Abstract: A semiconductor package includes a semiconductor element, a wiring structure, an encapsulation structure, and a solder ball. The semiconductor element includes a plurality of pins. A side of the wiring structure is electrically connected to the plurality of pins of the semiconductor element. The wiring structure includes at least two first wiring layers. A first insulating layer is disposed between adjacent two first wiring layers of the at least two first wiring layers. The first insulating layer includes a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The encapsulation structure at least partially surrounds the semiconductor element. The solder ball is located on a side of the wiring structure away from the semiconductor element. The solder ball is electrically connected to the at least two first wiring layers.

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