公开(公告)号：US20200312772A1

公开(公告)日：2020-10-01

申请号：US16441501

申请日：2019-06-14

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Feng QIN ,  Jine LIU ,  Xiaohe LI ,  Tingting CUI ,  Yuan DING

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a redistribution layer, a soldering pad group, and bare chips. Connecting posts is formed on a side of the bare chips. The encapsulating layer covers the bare chips and the connecting posts, while exposes a side of the connecting posts away from the bare chips. The redistribution layer on the connecting posts includes a first redistribution wire, a second redistribution wire, and a third redistribution wire. The first redistribution wire and the second redistribution wire are electrically connected to at least one connecting post respectively, and the third redistribution layer is electrically connected to remaining connecting posts. The soldering pad group on the redistribution layer includes an input soldering pad electrically connected to the first redistribution wire and an output soldering pad electrically connected to the second redistribution wire.