公开(公告)号：US09208734B2

公开(公告)日：2015-12-08

申请号：US14083304

申请日：2013-11-18

Applicant: Shanghai Tianma Micro-Electronics Co., Ltd.

Inventor： Dong Qian ,  Changho Tseng

IPC: G11C19/00 ,  G09G3/36 ,  G11C19/28 ,  G11C19/18 ,  H03K17/16

CPC classification number: G09G3/3611 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28 ,  H03K17/161

Abstract: A shift register includes an input terminal, an output terminal, a first clock signal terminal, a second clock signal terminal, a first level signal terminal, a second level terminal, a first capacitor and a second capacitor, and five transistors. The five transistors are controlled by first and second clock signals applied to the respective first and second signal terminals to shift a signal received from the input terminal to the output terminal with a half cycle period delay while maintaining a stable level of the shifted signal at the output terminal.

Abstract translation: 移位寄存器包括输入端子，输出端子，第一时钟信号端子，第二时钟信号端子，第一电平信号端子，第二电平端子，第一电容器和第二电容器以及五个晶体管。 五个晶体管由施加到相应的第一和第二信号端子的第一和第二时钟信号控制，以使半周期周期延迟将从输入端子接收的信号移位到输出端子，同时保持位移信号的稳定电平 输出端子。

公开(公告)号：US20140079176A1

公开(公告)日：2014-03-20

申请号：US14083304

申请日：2013-11-18

Applicant: Shanghai Tianma Micro-Electronics Co., Ltd.

Inventor： Dong QIAN ,  Changho Tseng

IPC: G09G3/36 ,  H03K17/16

CPC classification number: G09G3/3611 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28 ,  H03K17/161

Abstract: A shift register includes an input terminal, an output terminal, a first clock signal terminal, a second clock signal terminal, a first level signal terminal, a second level terminal, a first capacitor and a second capacitor, and five transistors. The five transistors are controlled by first and second clock signals applied to the respective first and second signal terminals to shift a signal received from the input terminal to the output terminal with a half cycle period delay while maintaining a stable level of the shifted signal at the output terminal.

Abstract translation: 移位寄存器包括输入端子，输出端子，第一时钟信号端子，第二时钟信号端子，第一电平信号端子，第二电平端子，第一电容器和第二电容器以及五个晶体管。 五个晶体管由施加到相应的第一和第二信号端子的第一和第二时钟信号控制，以使半周期周期延迟将从输入端子接收的信号移位到输出端子，同时保持位移信号的稳定电平 输出端子。