Abstract:
The disclosure relates to an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes a plurality of data lines and a plurality of first gate lines, a plurality of first pixel units and a plurality of second pixel units; a plurality of second gate lines; a first TFT and a second TFT, where a first electrode of the first TFT is disposed at one side of the second gate line, the gate and the second electrode of the first TFT is disposed at the other side of the second gate line, the gate, the first electrode, the second electrode and the active layer of each second TFT are disposed at the same side of the second gate line, where the first electrodes of the first TFT and the second TFT are electrically connected to the date lines respectively.
Abstract:
An organic light-emitting display panel, divided into a display region and a non-display region surrounding the display region, includes a substrate; an array layer formed over the substrate; a pixel defining layer formed on the surface of the array layer away from the substrate; and a plurality of organic light-emitting devices formed in a plurality of openings of the pixel defining layer. The plurality of organic light-emitting devices are disposed in the display region, and each organic light-emitting device includes an anode, an organic light-emitting layer, and a cathode sequentially formed on the substrate. The organic light-emitting display panel also includes a plurality of support units disposed in the non-display region. At least one support unit of the plurality of support units is disposed on the surface of the pixel defining layer away from the substrate.
Abstract:
The disclosure relates to an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes a plurality of data lines and a plurality of first gate lines, a plurality of first pixel units and a plurality of second pixel units; a plurality of second gate lines; a first TFT and a second TFT, where a first electrode of the first TFT is disposed at one side of the second gate line, the gate and the second electrode of the first TFT is disposed at the other side of the second gate line, the gate, the first electrode, the second electrode and the active layer of each second TFT are disposed at the same side of the second gate line, where the first electrodes of the first TFT and the second TFT are electrically connected to the date lines respectively.
Abstract:
The present disclosure provides an organic light-emitting pixel driving circuit. The organic light-emitting pixel driving circuit includes first driving transistor, having first terminal electrically connected to first node, second terminal electrically connected to second node, and control terminal electrically connected to third node, second driving transistor, having first terminal electrically connected to the second node, second terminal electrically connected to fourth node, and control terminal electrically connected to the third node; first switch transistor, having first terminal electrically connected to data signal terminal, and second terminal electrically connected to the first node, second switch transistor, having first terminal electrically connected to the data signal terminal, and second terminal electrically connected to the fourth node; third switch transistor, having first terminal electrically connected to the third node, and second terminal electrically connected to the second node; and storage device electrically connected to the third node.
Abstract:
The present disclosure provides an organic light-emitting pixel driving circuit. The organic light-emitting pixel driving circuit includes first driving transistor, having first terminal electrically connected to first node, second terminal electrically connected to second node, and control terminal electrically connected to third node, second driving transistor, having first terminal electrically connected to the second node, second terminal electrically connected to fourth node, and control terminal electrically connected to the third node; first switch transistor, having first terminal electrically connected to data signal terminal, and second terminal electrically connected to the first node, second switch transistor, having first terminal electrically connected to the data signal terminal, and second terminal electrically connected to the fourth node; third switch transistor, having first terminal electrically connected to the third node, and second terminal electrically connected to the second node; and storage device electrically connected to the third node.