Abstract:
A gate drive circuit is disclosed. The gate drive circuit includes shift register units connected with gate lines. The gate drive circuit also includes clock signal lines to provide clock signals. A trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p−1)-th shift register unit. An end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2M−1)-th shift register unit, low level signal terminals are connected with a first low level signal line, and reset signal terminals are connected with a reset signal line. In addition, forward scan signal terminals are connected with a first scan signal line, and backward scan signal terminals are connected with a second scan signal line.
Abstract:
Provided are a display panel and a spliced display device. The display panel includes pixel rows and spacing areas. The pixel rows include a type-A pixel row adjacent to a first panel edge and type-B pixel rows including a first type-B pixel row. The spacing areas correspond to and are adjacent to the type-B pixel rows, and close to the first panel edge. The pixel row includes light-emitting devices and pixel circuits. The pixel circuit includes a first part and a second part. In the type-A pixel row, the first part is located at a side of the light-emitting device close to the first panel edge, and the second part is located in the spacing area corresponding to the first type-B pixel row. In at least one type-B pixel row, the pixel circuit is located at a side of the light-emitting device close to the first panel edge.
Abstract:
The present disclosure discloses a gate driver, an array substrate, a display panel and a display device so as to address problems in the gate driver that some shift register units become abnormal so that a succeeding shift register unit depending upon the shift register unit may not be triggered and consequently the entire GOA circuit may operate improperly and even become inoperative. The gate driver includes N shift register units, each of which is connected with respective one of N gate lines of a display panel, and a plurality of gate units. While a gate unit is enabled, the gate unit is configured to provide a current gate line with an output signal of a corresponding shift register unit connected to a preceding gate line and/or a corresponding shift register unit connected to a succeeding gate line.
Abstract:
A display panel including a display area, subpixels located in the display area, and a shift register. The shift register includes a plurality of stages of shift units that are cascaded. Each of the plurality of stages of shift units is electrically connected to one control signal line of a plurality of control signal lines and at least two of the subpixels respectively and is configured to output a driving signal to the at least two of the subpixels in response to a control signal. The shift register is located in the display area, and at least one control signal line of the plurality of control signal lines is located in the display area.
Abstract:
A color filter substrate, a display panel and a display device are provided. The color filter substrate includes a first substrate, a black matrix layer located on the first substrate, and an electrostatic discharge wire layer located on the black matrix layer and connected to the black matrix layer. In the color filter substrate, the display panel and the display device, the electrostatic discharge wire layer is arranged on the black matrix layer of the color filter substrate. Hence, static electricity in the color filter substrate is discharged via the electrostatic discharge wire layer, and accordingly, the static electricity may not be accumulated in the color filter substrate, thereby improving the quality and performance of a display.