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公开(公告)号：US11294716B2
公开(公告)日：2022-04-05
申请号：US16558697
申请日：2019-09-03
发明人： Wei Zhao , Xuehua Han , Fangfang Wu , Jin Yu
摘要： A processing system includes at least one core, at least one accelerator function unit (AFU) and an acceleration interface. The unit runs a plurality of processes and develops at least one task queue corresponding to each of the processes. The core generates several command packets and pushes them into the corresponding task queue. The AFU are used to execute the command packets. The acceleration interface is arranged between the AFU and the core to receive an acceleration interface instruction from the processing core, and establish a bit map based on the acceleration interface instruction. The bit map is used to indicate which task queue contains the command packets that have been generated.
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公开(公告)号：US10862508B1
公开(公告)日：2020-12-08
申请号：US16593056
申请日：2019-10-04
发明人： Wei Zhao , Zongpu Qi , Zheng Wang , Jiamin Situ
摘要： A method for encoding and compressing a bit stream is provided. The method includes: receiving a bit stream; determining whether a first number of bits that are consecutive and identical in the bit stream is greater than or equal to a first preset value; and when the first number is greater than or equal to the first preset value, the first number of bits are encoded as a first code in a first encoding way, wherein the first code is composed of a first prefix and a first suffix, and the first prefix represents what the consecutive bits are and the first suffix represents the first number.
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公开(公告)号：US10310761B2
公开(公告)日：2019-06-04
申请号：US15797617
申请日：2017-10-30
发明人： Zongpu Qi , Di Hu , Wei Zhao , Zheng Wang , Xiaoyang Li
IPC分类号： G06F3/06
摘要： A storage device includes a memory unit, an access monitor, and a memory configurator. The memory unit includes a plurality of memory blocks. The access monitor is configured to monitor whether an access mode of the memory unit is a continuous-access mode or a random-access mode, to generate a monitor signal. The memory configurator configures, according to the monitor signal, any of the memory blocks to be either in a cache mode or a SRAM state to generate a configuration signal.
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公开(公告)号：US11256633B2
公开(公告)日：2022-02-22
申请号：US16558618
申请日：2019-09-03
发明人： Xiaoyang Li , Chen Chen , Zongpu Qi , Tao Li , Xuehua Han , Wei Zhao , Dongxue Gao
IPC分类号： G06F13/16 , G06F9/48 , G06F12/1027
摘要： A processing system includes at least one core, a plurality of accelerator function unit (AFU) and a memory access unit. The memory access unit includes at least one pipeline resource and an arbitrator. The core develops a plurality of tasks. Each of the AFU is used to execute at least one of the tasks which corresponds to several memory access requests. The arbitrator selects one of the AFUs using a round-robin method at each clock period to transmit a corresponding memory access request of the selected AFU to the pipeline resource, so that the selected AFU executes the memory access request through the pipeline resource to read or write data related to the task.
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公开(公告)号：US11216304B2
公开(公告)日：2022-01-04
申请号：US16558726
申请日：2019-09-03
发明人： Wei Zhao , Xuehua Han , Fangfang Wu , Jin Yu
摘要： A processing system includes at least one core, several accelerator function units (AFU) and a microcontroller. The core is utilized to operate several processes and develop at least one task queue corresponding to each of the processes. The processing core generates several command packets and pushes them into the corresponding task queue. The AFU executes the command packets. The microcontroller is arranged between the AFU and the core to dispatch the command packet to a corresponding AFU for execution. When the corresponding AFU executes the command packet of a specific process of the processes, the microcontroller assigns the corresponding AFU to execute other command packets in the task queue of the specific process at a higher priority.
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公开(公告)号：US11301297B2
公开(公告)日：2022-04-12
申请号：US16558668
申请日：2019-09-03
发明人： Xiaoyang Li , Chen Chen , Zongpu Qi , Tao Li , Xuehua Han , Wei Zhao , Dongxue Gao
摘要： A processing system includes at least one core, at least one accelerator function unit (AFU), a microcontroller, and a memory access unit. The AFU and the core share a plurality of virtual addresses to access a memory. The microcontroller is coupled between the core and the AFU. The core develops and stores a task in one of the virtual addresses. The microcontroller analyzes the task and dispatches the task to the AFU. The AFU accesses the virtual address indicating where the task is stored through the memory access unit to executes the task.
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公开(公告)号：US11263139B2
公开(公告)日：2022-03-01
申请号：US15797527
申请日：2017-10-30
IPC分类号： G06F12/0875 , G06F12/0888 , G06F12/0811 , G06F12/084
摘要： A processing system includes a cache, a host memory, a CPU and a hardware accelerator. The CPU accesses the cache and the host memory and generates at least one instruction. The hardware accelerator operates in a non-temporal access mode or a temporal access mode according to the access behavior of the instruction. The hardware accelerator accesses the host memory through an accelerator interface when the hardware accelerator operates in the non-temporal access mode, and accesses the cache through the accelerator interface when the hardware accelerator operates in the temporal access mode.
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公开(公告)号：US10929187B2
公开(公告)日：2021-02-23
申请号：US16558637
申请日：2019-09-03
发明人： Xiaoyang Li , Chen Chen , Zongpu Qi , Tao Li , Xuehua Han , Wei Zhao , Dongxue Gao
摘要： A processing system includes a core, at least one accelerator function unit (AFU) and an accelerator interface. The core is utilized to develop at least one task. The AFU is utilized to execute the task. The accelerator interface is arranged between the core and the AFU to receive an accelerator interface instruction transmitted by the processing core and instruct the AFU to execute the task according to the accelerator interface instruction.
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