公开(公告)号：US20160282693A1

公开(公告)日：2016-09-29

申请号：US15172627

申请日：2016-06-03

Applicant: Sharp Kabushiki Kaisha

Inventor： Isao OGASAWARA ,  Takaharu YAMADA ,  Masahiro YOSHIDA ,  Satoshi HORIUCHI ,  Shinya TANAKA ,  Tetsuo KIKUCHI

IPC: G02F1/1362 ,  H01L27/12 ,  G02F1/1333 ,  G02F1/1339 ,  G02F1/1343 ,  G02F1/1345

CPC classification number: G02F1/136286 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/13452 ,  G02F1/13454 ,  H01L27/1222 ,  H01L27/124

Abstract: An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.

Abstract translation: 本发明的实施例提供了一种TFT阵列基板，其中TFT元件和与TFT元件相对应的像素电极在矩阵上排列在绝缘基板上，该TFT阵列基板包括：由第一金属材料制成的栅极总线 ; 由第二金属材料制成的源总线; 由第三金属材料制成的像素电极; 由第一金属材料制成的时钟布线; 由第二金属材料制成的分支布线; 以及由第三金属材料制成的连接导体，连接导体在周边区域的连接部分连接时钟布线和分支布线，所述连接部分具有分支布线通孔，该布线通孔使被覆盖的分支布线 与连接导体，并且至少部分地在平面图中与时钟布线重叠。

公开(公告)号：US20150301389A1

公开(公告)日：2015-10-22

申请号：US14438683

申请日：2013-11-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiro YOSHIDA ,  Isao OGASAWARA

IPC: G02F1/1345 ,  G02F1/1368 ,  G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/13454 ,  G02F1/1345 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/13456 ,  H01L27/1225

Abstract: On an active matrix substrate (5), metal electrodes (44) are provided below pixel electrodes (19). At least portions of a plurality of second thin-film transistors (second switching elements) (23b) are covered by light shielding films formed from the metal electrodes (44). The metal electrodes (light shielding films) (44) are covered by an interlayer insulating film (33) and an electrode film (CSa) of an auxiliary capacitance electrode (common electrode) (CS).

Abstract translation: 在有源矩阵基板（5）上，金属电极（44）设置在像素电极（19）的下方。 多个第二薄膜晶体管（第二开关元件）（23b）的至少一部分被由金属电极（44）形成的遮光膜覆盖。 金属电极（遮光膜）（44）被辅助电容电极（公共电极）（CS）的层间绝缘膜（33）和电极膜（CSa）覆盖。

公开(公告)号：US20200043958A1

公开(公告)日：2020-02-06

申请号：US16486840

申请日：2018-02-14

Applicant: Sharp Kabushiki Kaisha

Inventor： Satoshi HORIUCHI ,  Yoshihiro ASAI ,  Isao OGASAWARA ,  Masakatsu TOMINAGA ,  Yoshihito HARA

IPC: H01L27/12 ,  G09G3/36

Abstract: The present invention reduces a circuit scale of a driving circuit while maintaining a characteristic of the driving circuit. In a driving circuit of the present invention, a transistor (TRc) including a gate electrode, a semiconductor film (HF), and first and second conductive electrodes (S, D) is provided on an upper side of the substrate. The driving circuit further includes a first conductive film (21) provided in a layer lower than the gate electrode, a second conductive film (22) that serves as the gate electrode, and a first capacitor (C1) defined between the first conductive film (21) and the second conductive film (22).

公开(公告)号：US20170123249A1

公开(公告)日：2017-05-04

申请号：US15312004

申请日：2015-05-18

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masahiro YOSHIDA ,  Isao OGASAWARA ,  Yasuhiro MIMURA

IPC: G02F1/1368 ,  G02F1/1345 ,  G02F1/1362

CPC classification number: G02F1/136259 ,  G02F1/1345 ,  G02F1/13452 ,  G02F1/136204 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136254

Abstract: Inside of a region for inspection set outside a display region of an active matrix substrate, lead-out lines (27a to 27f) connected to data lines pass through in a column direction, and a control line for inspection (31) and six signal lines for inspection (32a to 32f) extend in a row direction. TFTs for inspection (51a to 51f) control a conduction state between the lead-out line and the corresponding signal line for inspection in accordance with a signal on the control line for inspection. Inside the region for inspection, three of the six signal lines for inspection are arranged on one side of the control line for inspection, and the remaining three are arranged on other side of the control line for inspection. One of the two adjacent lead-out lines is connected to one of the former signal lines for inspection via the TFT for inspection (51a, 51c, 51e), and the other is connected to one of the latter signal lines for inspection via the TFT for inspection (51b, 51d, 51f). This suppresses a disconnection, a leakage current, and a luminance unevenness of a screen for inspection.

公开(公告)号：US20160026052A1

公开(公告)日：2016-01-28

申请号：US14851413

申请日：2015-09-11

Applicant: Sharp Kabushiki Kaisha

Inventor： Isao OGASAWARA ,  Masahiro YOSHIDA

IPC: G02F1/1362 ,  G02F1/1345

CPC classification number: G02F1/136286 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F2001/13456

Abstract: Provided are a display device and a method of manufacturing same, whereby deterioration in image display quality due to display unevenness or shadowing is avoided. An open region is disposed in a source driver mounting region in a position thereof that corresponds to a remaining output region 15 of a source driver 4. Next, a common signal line 30, which connects an FPC connecting region 19 to a common transfer electrode 20a, is formed passing through the open region. It is thus possible to shorten the length of the common signal line 30, and to position the common transfer electrode 20a in a desired location. Consequently, variation in the common signal lag for each position on a common electrode is mitigated, making it possible to minimize image display unevenness. The width of the open region is also increased, allowing the width of the common signal line 30 to also be increased. Consequently, the load on the common signal line 30 can be reduced.

Abstract translation: 提供了一种显示装置及其制造方法，从而避免了由于显示不均匀或阴影引起的图像显示质量的劣化。 在与驱动器4的剩余输出区域15相对应的位置上的源极驱动器安装区域中设置开放区域。接下来，将FPC连接区域19连接到公共转移电极20a的公共信号线30 形成穿过开放区域。 因此，可以缩短公共信号线30的长度，并将公共传输电极20a定位在期望的位置。 因此，减轻了公共电极上每个位置的公共信号滞后的变化，使得可以使图像显示不均匀性最小化。 开放区域的宽度也增加，允许公共信号线30的宽度也增加。 因此，可以减小公共信号线30上的负载。

公开(公告)号：US20190033648A1

公开(公告)日：2019-01-31

申请号：US16147949

申请日：2018-10-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiro YOSHIDA ,  Isao OGASAWARA ,  Satoshi HORIUCHI ,  Takaharu YAMADA

IPC: G02F1/1345 ,  G02F1/1362 ,  G02F1/1339

Abstract: In the present liquid crystal display device, a conventional first auxiliary capacitance trunk line 430 is formed to be narrow, and a second auxiliary capacitance trunk line 440 is additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole, so that the shift register is not overlaid with a seal material. Moreover, the extent of an area overlaid with a seal material within a wiring area for providing signals to the shift register can be reduced.

公开(公告)号：US20160131933A1

公开(公告)日：2016-05-12

申请号：US14988801

申请日：2016-01-06

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiro YOSHIDA ,  Isao OGASAWARA ,  Satoshi HORIUCHI ,  Takaharu YAMADA

IPC: G02F1/1345 ,  G02F1/1362 ,  G02F1/1339

CPC classification number: G02F1/13454 ,  G02F1/1339 ,  G02F1/1345 ,  G02F1/136213 ,  G02F1/136286

Abstract: In the present liquid crystal display device, a conventional first auxiliary capacitance trunk line 430 is formed to be narrow, and a second auxiliary capacitance trunk line 440 is additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole, so that the shift register is not overlaid with a seal material. Moreover, the extent of an area overlaid with a seal material within a wiring area for providing signals to the shift register can be reduced.

Abstract translation: 在本液晶显示装置中，常规的第一辅助电容干线430形成为窄，并且第二辅助电容干线440被附加地设置并设置在与基板的周边最接近的位置。 因此，移位寄存器可以从衬底的周边远离，而不会增加整个框架区域，从而移位寄存器不会被密封材料覆盖。 此外，可以减少用于向移位寄存器提供信号的布线区域内用密封材料重叠的区域的范围。

公开(公告)号：US20150364396A1

公开(公告)日：2015-12-17

申请号：US14764198

申请日：2014-01-24

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Yoshihiro ASAI ,  Katsuhiro OKADA ,  Isao OGASAWARA ,  Masahiro YOSHIDA

IPC: H01L23/31 ,  H01L27/12 ,  H01L29/786 ,  G09G3/36

CPC classification number: H01L23/3142 ,  G02F1/13336 ,  G02F1/13454 ,  G09G3/36 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2300/0426 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78633 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a liquid crystal display device (1) according to one aspect of the present invention, each of a first gate driver (17) supplying a gate signal to a first gate line (10) of a first display part (8) and a second gate driver (18) supplying a gate signal to a second gate line (13) of a second display part (9) are constituted to comprise a transistor formed on one surface of an array substrate (2).

Abstract translation: 在根据本发明的一个方面的液晶显示装置（1）中，向第一显示部分（8）的第一栅极线（10）提供栅极信号的第一栅极驱动器（17）和第二栅极驱动器 向第二显示部分（9）的第二栅极线（13）提供栅极信号的栅极驱动器（18）构成为包括形成在阵列基板（2）的一个表面上的晶体管。

公开(公告)号：US20140267969A1

公开(公告)日：2014-09-18

申请号：US14291937

申请日：2014-05-30

Applicant: Sharp Kabushiki Kaisha

Inventor： Isao OGASAWARA ,  Takaharu YAMADA ,  Masahiro YOSHIDA ,  Satoshi HORIUCHI ,  Shinya TANAKA ,  Tetsuo KIKUCHI

IPC: G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/136286 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/13452 ,  G02F1/13454 ,  H01L27/1222 ,  H01L27/124

Abstract: An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.

Abstract translation: 本发明的实施例提供了一种TFT阵列基板，其中TFT元件和与TFT元件相对应的像素电极在矩阵上排列在绝缘基板上，该TFT阵列基板包括：由第一金属材料制成的栅极总线 ; 由第二金属材料制成的源总线; 由第三金属材料制成的像素电极; 由第一金属材料制成的时钟布线; 由第二金属材料制成的分支布线; 以及由第三金属材料制成的连接导体，连接导体在周边区域的连接部分连接时钟布线和分支布线，所述连接部分具有分支布线通孔，该布线通孔使被覆盖的分支布线 与连接导体，并且至少部分地在平面图中与时钟布线重叠。

公开(公告)号：US20220326561A1

公开(公告)日：2022-10-13

申请号：US17712269

申请日：2022-04-04

Applicant: Sharp Kabushiki Kaisha

Inventor： Yoshihiro ASAI ,  Isao OGASAWARA

IPC: G02F1/1362 ,  G09G3/36

Abstract: A display device includes a display substrate, a plurality of source drive circuit elements, gate drive circuits, and a plurality of gate connection lines. The plurality of gate connection lines pass through inter-element regions between the source drive circuit elements in plan view, and pass through mounting regions. Gate terminals connected to the gate connection lines are formed at positions facing the inter-element regions in a direction from the inter-element regions toward an FPC (Y2 direction).