公开(公告)号：US20230307465A1

公开(公告)日：2023-09-28

申请号：US18199142

申请日：2023-05-18

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Teruyuki UEDA ,  Yoshihito HARA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA ,  Tetsuo KIKUCHI

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/127

Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.

公开(公告)号：US20210327911A1

公开(公告)日：2021-10-21

申请号：US17224166

申请日：2021-04-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L29/786

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

公开(公告)号：US20200303425A1

公开(公告)日：2020-09-24

申请号：US16820900

申请日：2020-03-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Masamitsu YAMANAKA ,  Teruyuki UEDA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/24 ,  H01L29/786 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1333

Abstract: A method for manufacturing an active matrix board includes (E) a step of forming a source contact hole and a drain contact hole in an interlayer insulating layer such that a portion of a source contact region of an oxide semiconductor layer and a portion of a drain contact region thereof are exposed and forming a connecting portion contact hole in the interlayer insulating layer and a lower insulating layer such that a portion of a lower conductive layer is exposed; and (F) a step of forming a source electrode, a drain electrode, and an upper conductive layer on the interlayer insulating layer; and the step (E) includes (e-1) a step of forming a photoresist film on the interlayer insulating layer and (e-2) a step of forming a photoresist layer in such a manner that the photoresist film is exposed to light using a multi-tone mask and is then developed.

公开(公告)号：US20190081077A1

公开(公告)日：2019-03-14

申请号：US16084568

申请日：2017-03-13

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hajime IMAI ,  Hisao OCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Toshikatsu ITOH ,  Teruyuki UEDA ,  Ryosuke GUNJI ,  Kengo HARA ,  Tohru DAITOH

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423

Abstract: An active matrix substrate includes a substrate, a TFT-containing layer which is supported on the substrate, and which includes a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes of the TFT, a metal wiring layer which is supported on the substrate and has a thickness of 400 nm or more, and an inorganic insulating layer which is thinner than the metal wiring layer, and is arranged on a substrate side of the metal wiring layer and is in contact with a lower surface of the metal wiring layer. The metal wiring layer has tensile stress and the inorganic insulating layer has compressive stress, and a ratio Sb/Sa of an absolute value Sb of a stress value of the inorganic insulating layer to an absolute value Sa of a stress value of the metal wiring layer is 0.6 or more and 1.7 or less.

公开(公告)号：US20140267969A1

公开(公告)日：2014-09-18

申请号：US14291937

申请日：2014-05-30

Applicant: Sharp Kabushiki Kaisha

Inventor： Isao OGASAWARA ,  Takaharu YAMADA ,  Masahiro YOSHIDA ,  Satoshi HORIUCHI ,  Shinya TANAKA ,  Tetsuo KIKUCHI

IPC: G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/136286 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/13452 ,  G02F1/13454 ,  H01L27/1222 ,  H01L27/124

Abstract: An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.

Abstract translation: 本发明的实施例提供了一种TFT阵列基板，其中TFT元件和与TFT元件相对应的像素电极在矩阵上排列在绝缘基板上，该TFT阵列基板包括：由第一金属材料制成的栅极总线 ; 由第二金属材料制成的源总线; 由第三金属材料制成的像素电极; 由第一金属材料制成的时钟布线; 由第二金属材料制成的分支布线; 以及由第三金属材料制成的连接导体，连接导体在周边区域的连接部分连接时钟布线和分支布线，所述连接部分具有分支布线通孔，该布线通孔使被覆盖的分支布线 与连接导体，并且至少部分地在平面图中与时钟布线重叠。

公开(公告)号：US20220005839A1

公开(公告)日：2022-01-06

申请号：US17364939

申请日：2021-07-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Tohru DAITOH ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tetsuo KIKUCHI

IPC: H01L27/12

Abstract: An active matrix substrate includes a first TFT and a second TFT, each of TFTs includes an oxide semiconductor layer and a gate electrode arranged on the oxide semiconductor layer with a gate insulating layer therebetween, in which in the first TFT, in the oxide semiconductor layer, in at least a part of a first region covered with the gate electrode with the gate insulating layer interposed therebetween, a layered structure including a high mobility oxide semiconductor film having a relatively high mobility and a low mobility oxide semiconductor film placed on the high mobility oxide semiconductor film and having a lower mobility than the high mobility oxide semiconductor film is provided, and in the second TFT, in a first region of the oxide semiconductor layer, throughout, of the high mobility oxide semiconductor film and the low mobility oxide semiconductor film, one oxide semiconductor film is provided, and the other oxide semiconductor film is not provided.

公开(公告)号：US20210273107A1

公开(公告)日：2021-09-02

申请号：US17183411

申请日：2021-02-24

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/49 ,  G02F1/1368

Abstract: An active matrix substrate has pixel regions, and includes a substrate, pixel TFTs disposed to respectively correspond to the pixel regions, and pixel electrodes electrically connected to the pixel TFTs. The pixel TFTs are each a top gate structure TFT that has an oxide semiconductor layer, a gate insulating layer on the oxide semiconductor layer, and a gate electrode opposing the oxide semiconductor layer with the gate insulating layer therebetween. The gate insulating layer is formed of silicon oxide and includes a lower layer contacting the oxide semiconductor layer, and an upper layer on the lower layer. The lower layer H/N ratio of hydrogen atoms to nitrogen atoms in the lower layer is 1.5 to 5.0. The upper layer H/N ratio of hydrogen atoms to nitrogen atoms in the upper layer is 0.9 to 2.0. The lower layer H/N ratio is larger than the upper layer H/N ratio.

公开(公告)号：US20210183899A1

公开(公告)日：2021-06-17

申请号：US17118666

申请日：2020-12-11

Applicant: Sharp Kabushiki Kaisha

Inventor： Hajime IMAI ,  Tohru DAITOH ,  Teruyuki UEDA ,  Yoshihito HARA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA ,  Tetsuo KIKUCHI

IPC: H01L27/12

Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.

公开(公告)号：US20210036158A1

公开(公告)日：2021-02-04

申请号：US16493803

申请日：2018-03-08

Applicant: Sharp Kabushiki Kaisha

Inventor： Setsuji NISHIMIYA ,  Tohru DAITOH ,  Masahiko SUZUKI ,  Kengo HARA ,  Hajime IMAI ,  Toshikatsu ITOH ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Teruyuki UEDA

IPC: H01L29/786 ,  H01L29/24 ,  H01L21/02 ,  H01L21/477 ,  H01L21/467 ,  H01L29/66

Abstract: A semiconductor device (100) includes a TFT (10) supported on a substrate (11), wherein the TFT (10) includes a gate electrode (12g), a gate insulating layer (14) that covers the gate electrode (12g), and an oxide semiconductor layer (16) that is formed on the gate insulating layer (14). The oxide semiconductor layer 16 has a layered structure including a first oxide semiconductor layer (16a) in contact with the gate insulating layer (14) and a second oxide semiconductor layer (16b) layered on the first oxide semiconductor layer (16a). The first oxide semiconductor layer (16a) and the second oxide semiconductor layer (16b) both include In, Ga and Zn; an In atomic ratio of the first oxide semiconductor layer (16a) is greater than a Zn atomic ratio thereof, and an In atomic ratio of the second oxide semi-conductor layer (16b) is smaller than a Zn atomic ratio thereof; and the oxide semiconductor layer (16) has a side surface of a forward tapered shape.

公开(公告)号：US20200287054A1

公开(公告)日：2020-09-10

申请号：US16808463

申请日：2020-03-04

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Yoshimasa CHIKAMA ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer positioned between the semiconductor layer and the gate electrode, and a source electrode and a drain electrode that are electrically connected to the semiconductor layer, wherein the semiconductor layer has a stacked layer structure including a first oxide semiconductor layer including In, Ga, Zn, and Sn, and a second oxide semiconductor layer including In, Ga, Zn, and Sn, having a lower mobility than the first oxide semiconductor layer, and disposed on the first oxide semiconductor layer so as to be in direct contact with the first oxide semiconductor layer, the first and the second oxide semiconductor layers are amorphous, and a Sn atomic ratio R1 relative to all metal elements in the first oxide semiconductor layer and a Sn atomic ratio R2 relative to all metal elements in the second oxide semiconductor layer satisfy 0.8×R1≤R2≤1.2×R1.