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公开(公告)号：US07983362B2
公开(公告)日：2011-07-19
申请号：US12100996
申请日：2008-04-10
IPC分类号： H04L27/00
CPC分类号： H03K3/356139 , G11C7/1066 , G11C7/22
摘要： Receiver architectures and bias circuits for a data processor are provided. A receiver architecture includes a linear receiver having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver compares the DQ signal to the reference voltage, and generates the differential output signal in response to the comparison. A sense amplifier is coupled to the linear receiver. The sense amplifier has input nodes connected to the output nodes of the linear receiver, and an output node for a binary output signal having voltage characteristics compatible with the processor. The sense amplifier transforms the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver to set operating characteristics of the linear receiver.
摘要翻译： 提供了数据处理器的接收机架构和偏置电路。 接收器架构包括具有用于数据（DQ）信号的第一输入节点，用于参考电压的第二输入节点和用于差分输出信号的输出节点的线性接收器。 线性接收器将DQ信号与参考电压进行比较，并响应于比较而产生差分输出信号。 读出放大器耦合到线性接收器。 读出放大器具有连接到线性接收器的输出节点的输入节点和具有与处理器兼容的电压特性的二进制输出信号的输出节点。 读出放大器将差分输出信号转换为二进制输出信号。 接收机架构还包括耦合到线性接收机的编程架构以设置线性接收机的操作特性。
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2.发明授权公开(公告)号：US07826279B2
公开(公告)日：2010-11-02
申请号：US12100999
申请日：2008-04-10
IPC分类号： G11C7/00
CPC分类号： G06F13/4243
摘要： Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture for a computer processor includes a first linear receiver stage configured to receive a first input, a second input, and a first bias voltage. The first linear receiver stage is configured to generate a first differential output signal in response to a comparison between the first input and the second input. The first differential output signal has a specified programmable voltage swing that is influenced by the first bias voltage. The receiver architecture also includes a first programmable bias circuit coupled to the first linear receiver stage. The first programmable bias circuit is configured to generate the first bias voltage.
摘要翻译： 提供了数据处理器的接收机架构和相关偏置电路。 用于计算机处理器的接收器架构的一个实施例包括被配置为接收第一输入，第二输入和第一偏置电压的第一线性接收器级。 第一线性接收机级被配置为响应于第一输入和第二输入之间的比较而产生第一差分输出信号。 第一差分输出信号具有受第一偏置电压影响的指定可编程电压摆幅。 接收机架构还包括耦合到第一线性接收机级的第一可编程偏置电路。 第一可编程偏置电路被配置为产生第一偏置电压。
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公开(公告)号：US07652937B2
公开(公告)日：2010-01-26
申请号：US12100979
申请日：2008-04-10
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G11C7/10
摘要： Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes three linear receiver stages coupled in series. The first stage receives a differential data strobe (DQS) input signal associated with a plurality of data (DQ) signals, and the first stage has a first programmable swing voltage associated therewith. The second stage has a programmable shift voltage associated therewith, and the third stage has a second programmable swing voltage associated therewith. The receiver architecture also includes a programming architecture coupled to the first stage, the second stage, and the third stage. The programming architecture is configured to set the first programmable swing voltage, the programmable shift voltage, and the second programmable swing voltage.
摘要翻译： 提供了数据处理器的接收机架构和相关偏置电路。 接收机架构的一个实施例包括串联耦合的三个线性接收机级。 第一级接收与多个数据（DQ）信号相关联的差分数据选通（DQS）输入信号，并且第一级具有与其相关联的第一可编程摆幅电压。 第二级具有与其相关联的可编程移位电压，并且第三级具有与其相关联的第二可编程摆幅电压。 接收器架构还包括耦合到第一阶段，第二阶段和第三阶段的编程架构。 编程架构被配置为设置第一可编程摆幅电压，可编程移位电压和第二可编程摆幅电压。
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4.发明授权Receiver circuit having adaptive equalizer with characteristics determined by signal envelope measurement and method therefor 失效具有自适应均衡器的接收机电路，具有由信号包络测量确定的特性及其方法
公开(公告)号：US5796778A
公开(公告)日：1998-08-18
申请号：US534228
申请日：1995-09-26
CPC分类号： H04B3/145
摘要： Circuitry, and an associated method, for a receiver which receives data signals transmitted upon a non-ideal transmission channel. The circuitry includes an equalizer circuit and a variable gain amplifier circuit together operable to counteract the effects of the signal degradation. Characteristics of the equalizer circuit and of the amplifier circuit are together selected responsive to detection of the signal envelope of the data signal.
摘要翻译： 电路和相关方法，用于接收在非理想传输信道上发送的数据信号的接收机。 电路包括均衡器电路和可变增益放大器电路，可一起可以抵消信号劣化的影响。 响应于数据信号的信号包络的检测，一起选择均衡器电路和放大器电路的特性。
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