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公开(公告)号：US08848001B2
公开(公告)日：2014-09-30
申请号：US13070597
申请日：2011-03-24
申请人： Sheng-Chao Liu , Yao-Jen Hsieh , Ching-Huan Lin
发明人： Sheng-Chao Liu , Yao-Jen Hsieh , Ching-Huan Lin
CPC分类号： G09G3/344 , G09G2300/0842 , G09G2310/061 , G09G2320/0252
摘要： An exemplary driving method is adapted for a bistable display device including a pixel array. The pixel array includes a plurality of first pixels and a plurality of second pixels arranged in a predetermined manner. The driving method includes the following steps of: during a first time period, providing the first pixels with a first pixel voltage for black insertion and providing the second pixels with a second pixel voltage different from the first pixel voltage; during a second time period following the first time period, providing the first pixels with the second pixel voltage for white insertion and maintaining the second pixels provided with the second pixel voltage for white insertion; and during a third time period following the second time period, initiating the first pixels to display a gray scale image and providing the second pixels with the first pixel voltage for black insertion.
摘要翻译： 示例性驱动方法适用于包括像素阵列的双稳态显示装置。 像素阵列包括以预定方式布置的多个第一像素和多个第二像素。 该驱动方法包括以下步骤：在第一时间段期间，为第一像素提供用于黑插入的第一像素电压，并为第二像素提供不同于第一像素电压的第二像素电压; 在第一时间段之后的第二时间段期间，为第一像素提供用于白插入的第二像素电压，并保持提供有第二像素电压的第二像素进行白插入; 并且在第二时间段之后的第三时间段期间，启动第一像素以显示灰度图像，并为第二像素提供用于黑色插入的第一像素电压。
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公开(公告)号：US20110286571A1
公开(公告)日：2011-11-24
申请号：US13196322
申请日：2011-08-02
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3677
摘要： The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.
摘要翻译： 本发明涉及一种具有彼此串联电耦合的多个级的移位寄存器。 每个级包括第一和第二TFT晶体管。 第一TFT晶体管被电耦合到紧邻的前级的输出，电耦合到级的升压点的漏极和被配置为接收第一和第二控制信号中的一个的源极。 第二TFT晶体管被电耦合到紧邻的下一级的输出，漏极和源极分别电耦合第一晶体管的漏极和源极。
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公开(公告)号：US08294651B2
公开(公告)日：2012-10-23
申请号：US12508573
申请日：2009-07-24
IPC分类号： G09G3/36
CPC分类号： G02F1/136286 , G09G3/3655 , G09G2300/0456 , G09G2320/0673
摘要： A liquid crystal display (LCD) is provided. The LCD includes a display panel and a voltage supply device (VSD). The display panel includes a plurality of scan lines, a plurality of data lines disposed substantially perpendicularly with the scan lines, and a plurality of pixels. The pixels are respectively electrically connected with the corresponding data line and the corresponding scan line, and are arranged in an array. Each of the pixels includes a common line and a compensation line, wherein the common line is located in the transparent area to receive a common voltage, and the compensation line is located in the reflection area to receive a stable voltage. The VSD is coupled to the compensation line of each of the pixels for continuously and correspondingly providing the stable voltage to the compensation line of each of the pixels.
摘要翻译： 提供液晶显示器（LCD）。 LCD包括显示面板和电压供应装置（VSD）。 显示面板包括多条扫描线，与扫描线大致垂直设置的多条数据线以及多个像素。 像素分别与相应的数据线和对应的扫描线电连接，并且被排列成阵列。 每个像素包括公共线和补偿线，其中公共线位于透明区域中以接收公共电压，并且补偿线位于反射区域中以接收稳定的电压。 VSD耦合到每个像素的补偿线，用于连续地并相应地将稳定的电压提供给每个像素的补偿线。
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公开(公告)号：US08023611B2
公开(公告)日：2011-09-20
申请号：US12777845
申请日：2010-05-11
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3677
摘要： The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.
摘要翻译： 本发明涉及一种具有彼此串联电耦合的多个级的移位寄存器。 每个级包括第一和第二TFT晶体管。 第一TFT晶体管被电耦合到紧邻的前级的输出，电耦合到级的升压点的漏极和被配置为接收第一和第二控制信号中的一个的源极。 第二TFT晶体管被电耦合到紧邻的下一级的输出，漏极和源极分别电耦合第一晶体管的漏极和源极。
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公开(公告)号：US20100259701A1
公开(公告)日：2010-10-14
申请号：US12508573
申请日：2009-07-24
IPC分类号： G02F1/1343
CPC分类号： G02F1/136286 , G09G3/3655 , G09G2300/0456 , G09G2320/0673
摘要： A liquid crystal display (LCD) is provided. The LCD includes a display panel and a voltage supply device (VSD). The display panel includes a plurality of scan lines, a plurality of data lines disposed substantially perpendicularly with the scan lines, and a plurality of pixels. The pixels are respectively electrically connected with the corresponding data line and the corresponding scan line, and are arranged in an array. Each of the pixels includes a common line and a compensation line, wherein the common line is located in the transparent area to receive a common voltage, and the compensation line is located in the reflection area to receive a stable voltage. The VSD is coupled to the compensation line of each of the pixels for continuously and correspondingly providing the stable voltage to the compensation line of each of the pixels.
摘要翻译： 提供液晶显示器（LCD）。 LCD包括显示面板和电压供应装置（VSD）。 显示面板包括多条扫描线，与扫描线大致垂直设置的多条数据线以及多个像素。 像素分别与相应的数据线和对应的扫描线电连接，并且被排列成阵列。 每个像素包括公共线和补偿线，其中公共线位于透明区域中以接收公共电压，并且补偿线位于反射区域中以接收稳定的电压。 VSD耦合到每个像素的补偿线，用于连续地并相应地将稳定的电压提供给每个像素的补偿线。
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公开(公告)号：US20100059758A1
公开(公告)日：2010-03-11
申请号：US12405247
申请日：2009-03-17
IPC分类号： H01L33/00 , H01L29/786
CPC分类号： H01L27/1255 , G02F1/136286 , H01L27/1214
摘要： A tri-gate pixel structure includes three sub-pixel regions, three gate lines, a data line, three thin film transistors (TFTs), three pixel electrodes, and a common line. The gate lines are disposed along a first direction, and the data line is disposed along a second direction. The TFTs are disposed in the sub-pixel regions respectively, wherein each TFT has a gate electrode electrically connected to a corresponding gate line, a source electrode electrically connected to the data line, and a drain electrode. The three pixel electrodes are disposed in the three sub-pixel regions respectively, and each pixel electrode is electrically connected to the drain electrode of one TFT respectively. The common line crosses the gate lines and partially overlaps the three gate lines, and the common line and the three pixel electrodes are partially overlapped to respectively form three storage capacitors.
摘要翻译： 三栅极像素结构包括三个子像素区域，三个栅极线，数据线，三个薄膜晶体管（TFT），三个像素电极和公共线。 栅极线沿着第一方向设置，并且数据线沿着第二方向设置。 TFT分别设置在子像素区域中，其中每个TFT具有电连接到相应的栅极线的栅电极，与数据线电连接的源电极和漏电极。 三个像素电极分别设置在三个子像素区域中，并且每个像素电极分别电连接到一个TFT的漏电极。 公共线与栅极线交叉并且部分地重叠三条栅极线，并且公共线和三个像素电极部分地重叠以分别形成三个存储电容器。
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公开(公告)号：US08405787B2
公开(公告)日：2013-03-26
申请号：US12405247
申请日：2009-03-17
IPC分类号： G02F1/1343
CPC分类号： H01L27/1255 , G02F1/136286 , H01L27/1214
摘要： A tri-gate pixel structure includes three sub-pixel regions, three gate lines, a data line, three thin film transistors (TFTs), three pixel electrodes, and a common line. The gate lines are disposed along a first direction, and the data line is disposed along a second direction. The TFTs are disposed in the sub-pixel regions respectively, wherein each TFT has a gate electrode electrically connected to a corresponding gate line, a source electrode electrically connected to the data line, and a drain electrode. The three pixel electrodes are disposed in the three sub-pixel regions respectively, and each pixel electrode is electrically connected to the drain electrode of one TFT respectively. The common line crosses the gate lines and partially overlaps the three gate lines, and the common line and the three pixel electrodes are partially overlapped to respectively form three storage capacitors.
摘要翻译： 三栅极像素结构包括三个子像素区域，三个栅极线，数据线，三个薄膜晶体管（TFT），三个像素电极和公共线。 栅极线沿着第一方向设置，并且数据线沿着第二方向设置。 TFT分别设置在子像素区域中，其中每个TFT具有电连接到相应的栅极线的栅电极，与数据线电连接的源电极和漏电极。 三个像素电极分别设置在三个子像素区域中，并且每个像素电极分别电连接到一个TFT的漏电极。 公共线与栅极线交叉并且部分地重叠三条栅极线，并且公共线和三个像素电极部分地重叠以分别形成三个存储电容器。
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公开(公告)号：US08369479B2
公开(公告)日：2013-02-05
申请号：US13196322
申请日：2011-08-02
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3677
摘要： The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.
摘要翻译： 本发明涉及一种具有彼此串联电耦合的多个级的移位寄存器。 每个级包括第一和第二TFT晶体管。 第一TFT晶体管被电耦合到紧邻的前级的输出，电耦合到级的升压点的漏极和被配置为接收第一和第二控制信号中的一个的源极。 第二TFT晶体管被电耦合到紧邻的下一级的输出，漏极和源极分别电耦合第一晶体管的漏极和源极。
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公开(公告)号：US20100220082A1
公开(公告)日：2010-09-02
申请号：US12777845
申请日：2010-05-11
CPC分类号： G11C19/28 , G09G3/3677
摘要： The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.
摘要翻译： 本发明涉及一种具有彼此串联电耦合的多个级的移位寄存器。 每个级包括第一和第二TFT晶体管。 第一TFT晶体管被电耦合到紧邻的前级的输出，电耦合到级的升压点的漏极和被配置为接收第一和第二控制信号中的一个的源极。 第二TFT晶体管被电耦合到紧邻的下一级的输出，漏极和源极分别电耦合第一晶体管的漏极和源极。
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公开(公告)号：US08259895B2
公开(公告)日：2012-09-04
申请号：US13330489
申请日：2011-12-19
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A bidirectional shift register includes first, second, third and fourth control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes, where the shift register stages are grouped into a first section and a second section, where the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
摘要翻译： 双向移位寄存器包括用于分别提供第一，第二，第三和第四控制信号Bi1，Bi2，Bi3和Bi4的第一，第二，第三和第四控制信号总线，以及分别电连接的多个移位寄存器级， 每个移位寄存器级具有第一和第二输入节点，其中移位寄存器级被分组为第一部分和第二部分，其中第一部分中每个移位寄存器级的第一和第二输入节点电耦合到第一部分和第二部分， 分别用于接收第一和第二控制信号Bi1和Bi2的第二控制信号总线和第二部分中每个移位寄存器级的第一和第二输入节点电耦合到第三和第四控制信号总线， 第三和第四控制信号Bi3和Bi4。
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