公开(公告)号：US08522041B2

公开(公告)日：2013-08-27

申请号：US09896255

申请日：2001-06-28

申请人： Sherry Chu-Hsin Hsu ,  Praveen K. Kolli ,  Delmar Marr ,  Chao-Yuan Chang

发明人： Sherry Chu-Hsin Hsu ,  Praveen K. Kolli ,  Delmar Marr ,  Chao-Yuan Chang

IPC分类号： H04L9/00

CPC分类号： G06F21/72

摘要： A system and method for efficiently performing a data encryption operation in an electronic system preferably includes a processor that may initially create an encryption structure in a memory device. The encryption structure may preferably include one or more command structures for performing data encryption or decryption operations. The processor may subsequently program local control registers of a DMA engine with selected encryption information in response to a data encryption or decryption requirement. The processor may then instruct the DMA engine to perform the required data encryption or decryption operation. Next, the DMA engine may responsively copy one or more of the command structures from the memory device into local command registers that are coupled to the DMA engine. The DMA engine may then reference the foregoing control registers and command registers to thereby efficiently perform one or more data encryption or decryption operations. During the data encryption or decryption operations, the DMA engine may preferably provide source data from the memory device to an encryption module for encrypting or decrypting. The DMA engine may then responsively store the encrypted or decrypted data back into the memory device as destination data that may be subsequently provided to any appropriate destination entity that is coupled to the electronic system.

公开(公告)号：US06775730B2

公开(公告)日：2004-08-10

申请号：US09838102

申请日：2001-04-18

申请人： Delmar Marr ,  Harry Chue ,  Teiichi Shiga ,  James A. Chee

发明人： Delmar Marr ,  Harry Chue ,  Teiichi Shiga ,  James A. Chee

IPC分类号： G06F1324

CPC分类号： G06F9/4812

摘要： A system and method for implementing a flexible interrupt mechanism in an electronic system includes a processor that may initially execute an initialization routine for performing an interrupt configuration procedure. The foregoing interrupt configuration procedure may preferably be initiated when the processor programs a configuration register with certain selectable interrupt parameters that may be utilized to flexibly configure an interrupt module in the electronic system. Internal and external interrupt sources may then subsequently provide various interrupts to the configured interrupt module which may responsively detect and route the interrupts to the processor based upon interrupt information provided during the foregoing interrupt configuration procedure. The processor may then effectively service the interrupts during appropriate interrupt servicing procedures by utilizing corresponding interrupt handler routines.

摘要翻译： 用于在电子系统中实现灵活中断机制的系统和方法包括处理器，其可以初始地执行用于执行中断配置过程的初始化例程。 当处理器使用可用于灵活地配置电子系统中的中断模块的某些可选择的中断参数来编程配置寄存器时，可优选地启动上述中断配置过程。 内部和外部中断源随后可以随后向配置的中断模块提供各种中断，该中断模块可以基于在前述中断配置过程期间提供的中断信息来响应地检测和路由中断到处理器。 然后，处理器可以通过利用相应的中断处理程序在适当的中断服务过程中有效地服务中断。