公开(公告)号：US08522041B2

公开(公告)日：2013-08-27

申请号：US09896255

申请日：2001-06-28

申请人： Sherry Chu-Hsin Hsu ,  Praveen K. Kolli ,  Delmar Marr ,  Chao-Yuan Chang

发明人： Sherry Chu-Hsin Hsu ,  Praveen K. Kolli ,  Delmar Marr ,  Chao-Yuan Chang

IPC分类号： H04L9/00

CPC分类号： G06F21/72

摘要： A system and method for efficiently performing a data encryption operation in an electronic system preferably includes a processor that may initially create an encryption structure in a memory device. The encryption structure may preferably include one or more command structures for performing data encryption or decryption operations. The processor may subsequently program local control registers of a DMA engine with selected encryption information in response to a data encryption or decryption requirement. The processor may then instruct the DMA engine to perform the required data encryption or decryption operation. Next, the DMA engine may responsively copy one or more of the command structures from the memory device into local command registers that are coupled to the DMA engine. The DMA engine may then reference the foregoing control registers and command registers to thereby efficiently perform one or more data encryption or decryption operations. During the data encryption or decryption operations, the DMA engine may preferably provide source data from the memory device to an encryption module for encrypting or decrypting. The DMA engine may then responsively store the encrypted or decrypted data back into the memory device as destination data that may be subsequently provided to any appropriate destination entity that is coupled to the electronic system.

公开(公告)号：US06678749B2

公开(公告)日：2004-01-13

申请号：US09896403

申请日：2001-06-28

申请人： Praveen K. Kolli ,  Harry Chue ,  Mitsuaki Shiraga

发明人： Praveen K. Kolli ,  Harry Chue ,  Mitsuaki Shiraga

IPC分类号： G06F300

CPC分类号： G06F13/4027 ,  G06F3/0601 ,  G06F2003/0691

摘要： An apparatus and method for efficiently performing data transfer operations in an electronic system preferably includes a plurality of buffers that may store data and commands during execution of data transfer operations. Initially, at least a portion of a plurality of commands defining data transfer operations between a memory and peripheral devices may be temporarily stored in a command buffer associated with a processor interface. The processor interface may then issue commands directly to a memory interface, peripheral devices, and peripheral interfaces within the electronic system. Commands received by the memory interface may be temporarily stored in a command buffer associated with the memory interface. When a memory associated with the memory interface is ready, the memory interface may access the memory, and transfer data to or from one or more buffers associated with a peripheral device. Once the data is transferred to or from the buffers, then the memory interface may execute other commands stored in the command buffer. Execution of the first command does not have to be completed before the execution of a second command begins.

摘要翻译： 用于在电子系统中有效执行数据传送操作的装置和方法优选地包括可在数据传送操作执行期间存储数据和命令的多个缓冲器。 最初，定义存储器和外围设备之间的数据传送操作的多个命令的至少一部分可以临时存储在与处理器接口相关联的命令缓冲器中。 然后，处理器接口可以直接向电子系统内的存储器接口，外围设备和外围接口发出命令。 由存储器接口接收的命令可以临时存储在与存储器接口相关联的命令缓冲器中。 当与存储器接口相关联的存储器准备就绪时，存储器接口可以访问存储器，并且将数据传送到与外围设备相关联的一个或多个缓冲器中的数据。 一旦将数据传送到缓冲器或从缓冲器传输，则存储器接口可以执行存储在命令缓冲器中的其他命令。 在执行第二个命令开始之前，不必执行第一个命令。