公开(公告)号：US08816440B2

公开(公告)日：2014-08-26

申请号：US12984261

申请日：2011-01-04

申请人： Shigenobu Maeda ,  Jeong Hwan Yang

发明人： Shigenobu Maeda ,  Jeong Hwan Yang

IPC分类号： H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

摘要翻译： 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

公开(公告)号：US20050218455A1

公开(公告)日：2005-10-06

申请号：US11067836

申请日：2005-02-28

申请人： Shigenobu Maeda ,  Jeong Hwan Yang

发明人： Shigenobu Maeda ,  Jeong Hwan Yang

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/0922 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

摘要翻译： 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

公开(公告)号：US08710555B2

公开(公告)日：2014-04-29

申请号：US13417744

申请日：2012-03-12

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/06

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。

公开(公告)号：US20080117011A1

公开(公告)日：2008-05-22

申请号：US12021494

申请日：2008-01-29

申请人： Shigenobu Maeda ,  Jeong-hwan Yang

发明人： Shigenobu Maeda ,  Jeong-hwan Yang

IPC分类号： H01F17/00 ,  H01F5/00

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip inductor can include an outer inductor portion that separates an inner region of the inductor from an outer region of the inductor outside the inductor. An interconnect inductor portion is electrically coupled to the main inductor portion wherein the interconnect inductor portion can include extension portions that follow the contour of the adjacent portions of the outer inductor in the inner region of the inductor. An input path is coupled to the outer inductor portion through the extension portion and extends away from the inductor beneath the outer inductor portion on a first side thereof. An output path is coupled to the outer inductor portion through the extension portion and extends away from the inductor beneath the outer inductor portion on a second side of the inductor opposite the first side.

摘要翻译： 片上电感器可以包括外部电感器部分，其将电感器的内部区域与电感器外部的电感器的外部区域分开。 互连电感器部分电耦合到主电感器部分，其中互连电感器部分可以包括在电感器的内部区域中跟随外部电感器的相邻部分的轮廓的延伸部分。 输入路径通过延伸部分耦合到外部电感器部分，并且在外部电感器部分的第一侧上远离电感器延伸。 输出路径通过延伸部分耦合到外部电感器部分，并且在电感器的与第一侧相对的第二侧上远离电感器下方的电感器延伸。

公开(公告)号：US20120168828A1

公开(公告)日：2012-07-05

申请号：US13417744

申请日：2012-03-12

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/78

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

公开(公告)号：US08159006B2

公开(公告)日：2012-04-17

申请号：US12008232

申请日：2008-01-09

申请人： Shigenobu Maeda ,  Jeong-Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong-Hwan Yang ,  Junga Choi

IPC分类号： H01L29/06

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。 在SOI层上形成多栅极晶体管。 第一方向和第二方向相同，或者第一方向相对于第二方向成45度。 在本发明的另一方面，活性区域的顶表面和侧表面的交叉是弯曲的，进一步减少了NBTI。 在本发明的另一方面，多栅晶体管形成在体晶片的浅沟槽隔离区上。

公开(公告)号：US07956420B2

公开(公告)日：2011-06-07

申请号：US12004290

申请日：2007-12-20

申请人： Shigenobu Maeda ,  Jeong Hwan Yang

发明人： Shigenobu Maeda ,  Jeong Hwan Yang

IPC分类号： H01L29/94

CPC分类号： H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

公开(公告)号：US07456723B2

公开(公告)日：2008-11-25

申请号：US12021494

申请日：2008-01-29

申请人： Shigenobu Maeda ,  Jeong-hwan Yang

发明人： Shigenobu Maeda ,  Jeong-hwan Yang

IPC分类号： H01F5/00

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip inductor can include an outer inductor portion that separates an inner region of the inductor from an outer region of the inductor outside the inductor. An interconnect inductor portion is electrically coupled to the main inductor portion wherein the interconnect inductor portion can include extension portions that follow the contour of the adjacent portions of the outer inductor in the inner region of the inductor. An input path is coupled to the outer inductor portion through the extension portion and extends away from the inductor beneath the outer inductor portion on a first side thereof. An output path is coupled to the outer inductor portion through the extension portion and extends away from the inductor beneath the outer inductor portion on a second side of the inductor opposite the first side.

摘要翻译： 片上电感器可以包括外部电感器部分，其将电感器的内部区域与电感器外部的电感器的外部区域分开。 互连电感器部分电耦合到主电感器部分，其中互连电感器部分可以包括在电感器的内部区域中跟随外部电感器的相邻部分的轮廓的延伸部分。 输入路径通过延伸部分耦合到外部电感器部分，并且在外部电感器部分的第一侧上远离电感器延伸。 输出路径通过延伸部分耦合到外部电感器部分，并且在电感器的与第一侧相对的第二侧上远离电感器下方的电感器延伸。

公开(公告)号：US20050184283A1

公开(公告)日：2005-08-25

申请号：US11024616

申请日：2004-12-29

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/10 ,  H01L29/786 ,  H01L31/036 ,  H01L47/00

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。 在SOI层上形成多栅极晶体管。 第一方向和第二方向相同，或者第一方向相对于第二方向成45度。 在本发明的另一方面，活性区域的顶表面和侧表面的交叉是弯曲的，进一步减少了NBTI。 在本发明的另一方面，多栅晶体管形成在体晶片的浅沟槽隔离区上。

公开(公告)号：US09123811B2

公开(公告)日：2015-09-01

申请号：US13417706

申请日：2012-03-12

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/786 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。